Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Other

Jian-Hong Chen

Bang-Chein Ho

Jen-Chieh Shih

Sheng-Yueh Chang

Tzu-Yu Lin

Hsiao-Wei Yeh

Ting-Chun Liu

Bang-Chien Ho

Feng-Cheng Hsu

Mu-Tsang Lin

Jui-Fa Chang

Shu-Fang Jiang

Herng-Dar Hwu

Da-Jhong Ou Yang

Chon-Hwa Chu

Ie-Fun Lai

Wen-Sheng Chien

Ching-Yu Chang

Li-Te S Lin

Tsang-Jiuh Wu

Hua-Tai Lin

Ping-Hung Lu

Yih-Her Chang

Yusuke Takano

Li-Chih Chao

Mao-Song Lee

Wu-Bin Yuo

Chia-Hung Chung

Jyh-Wen Sheen

Bang-Ching Ho

Hsin-Herng Wang

Wen-Jen Tseng

Chih-An Lin

Muh-Lan Chen

Tien-Wen Wang

Wen-Jeng Lin

Yu-Yi Wu

Ho-May Lin

Bang Chein Ho

Ming-Chia Tai

Shyue-Sheng Lu

Chin-Chih Chen

Joseph W L Fang

Yao-Wen Wu

Dahchung Oweyang

Wen-Yuang Tsai

Tai-Sheng Yeh

Hung-Yuan Hsu

Teh Hu

Shu-Chieh Liuo

Hung Y Hsu

Shu-Yin Yang

Yi-Yu Wu

A photosensitive material for use in semiconductor manufacture comprises a copolymer that includes a plurality of photoresist chains and a plurality of hydrophobic chains, each hydrophobic chain attached to the end of one of the photoresist chains. The copolymer in response to externally applied energy will self-assemble to a photoresist layer and a hydrophobic layer.

Material and method for photolithography

A method of lithography patterning includes forming a first resist pattern on a substrate, the first resist pattern including a plurality of openings therein on the substrate; forming a second resist pattern on the substrate and within the plurality of openings of the first resist pattern, the second resist pattern including at least one opening therein on the substrate; and removing the first resist pattern to uncover the substrate underlying the first resist pattern.

Double patterning strategy for contact hole and trench in photolithography

The present invention includes a lithography method comprising forming a first patterned insist layer including at least one opening therein over a substrate. A water-soluble polymer layer is formed over the first patterned resist layer and the substrate, whereby a reaction occurs at the interface of the first patterned resist layer and the water-soluble polymer layer. The non-reacted water-soluble polymer layer is removed. Thereafter, a second patterned resist layer is formed over the substrate, wherein at least one portion of the second patterned resist layer is disposed within the at least one opening of the first patterned resist layer or abuts at least one portion of the first patterned resist layer. The substrate is thereafter etched using the first and second patterned resist layers as a mask.

High etch resistant material for double patterning

A method of making a semiconductor device including forming a first sacrificial layer over a first layer to be etched, the first sacrificial layer having a plurality of openings formed therethrough exposing a portion of the first layer; forming a first photoresist layer over the first sacrificial layer and filling the plurality of openings formed through the first sacrificial layer; forming a plurality of openings in the first photoresist layer, each one of the plurality of openings in the first photoresist layer overlying one of the openings in the first sacrificial layer and wherein each opening in the first sacrificial layer has a smaller cross-sectional area then the cross-sectional area of the overlying opening in the first photoresist layer; and etching the first layer through the openings in the first photoresist layer and the first sacrificial layer, comprising exposing the first layer to an etching material.

Method of making openings in a layer of a semiconductor device

An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor substrate. A protective layer is disposed on top of the dielectric layer and in the contact via hole, and subsequently forming as a recessed plug in the via, followed by etching to form a trench to complete formation of a dual damascene opening.

Method of forming a dual damascene structure

A method is described for reducing the space width of holes in a first resist pattern and simultaneously removing unwanted holes to change the pattern density in the resulting second pattern. This technique provides holes with a uniform space width as small as 100 nm or less that is independent of pattern density in the second pattern. A positive resist is patterned to form holes with a first pattern density and first space width. A water soluble negative resist is coated over the first resist and selectively exposed to form a second patterned layer consisting of water insoluble plugs in unwanted holes in the first pattern and a thin water insoluble layer on the first resist pattern in unexposed portions. The plugs may form dense and isolated hole arrays while the thin insoluble layer reduces space width to the same extent in remaining holes in the second pattern.

Water soluble negative tone photoresist

A method for forming a dual damascene structure in a semiconductor device manufacturing process where via plugs which may include a thickness portion of a plug filling material overlying the process surface is formed by diffusing an acid into a plug filling material layer followed by reacting the acid with the plug filling material layer to form a soluble portion which is then removed using a solvent. A remaining portion of the plug filling material is cured and a BARC layer may be formed over the process surface prior to patterning trenches in an overlying resist layer and forming a dual damascene structure.

Via plug formation in dual damascene process

A method for reducing a critical dimension of a photoresist pattern while improving a line spacing between distal end portions of pattern lines wherein the method includes providing a substrate including an overlying resist; exposing the resist to an activating light source; baking the resist in a first baking process followed by developing the resist in a first development process to form a first resist pattern; then baking the first resist pattern in a second baking process followed by developing the first resist pattern in a second development process to form a second resist pattern having reduced dimensions; and, then dry trimming the second resist pattern to form a final resist pattern with reduced dimensions compared to the second resist pattern.

Method for forming a finely patterned resist

A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.

Dual damascene process

An apparatus for fault detection and classification (FDC) specification management including a storage device and a process module. The storage device stores a specification management record and a chart profile record. The specification management record stores statistical algorithm settings of a parameter and the chart profile record stores chart frame and alarm condition information. The process module, which resides in a memory, receives a manipulation message corresponding to the specification management record, and accordingly manipulates the chart profile record.

Fault detection and classification (FDC) specification management apparatus and method thereof

In accordance with the objectives of the invention a new water soluble negative photoresist is provided for packing-and-unpacking (PAU) processing steps.

A system and method for automatic SPC chart generation including a storage device and a data acquisition module. The storage device stores a chamber management tree, a recipe window management tree, a parameter configuration table and multiple chart profile records. The data acquisition module, which resides in a memory, acquires multiple process events and parameter values corresponding to the process events and a process parameter, selects a relevant statistical algorithm, calculates a statistical value by applying the statistical algorithm to the parameter values, creates a new chart profile record and a parameter statistics record therein if the chart profile record is absent, and stores the statistical values and measured time in the parameter statistics record.

Automatic statistical process control (SPC) chart generation apparatus and method thereof

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Hsin-Chu, Taiwan

Jian-Hong Chen