Taiwan Semiconductor Manufacturing Comp. Ltd.

Jian-Hao Chen

Kuo-Feng Yu

Chia-Wei Chen

Shan-Mei Liao

Hui-Chi Chen

Yen-Ming Chen

Da-Yuan Lee

Wen-Hung Huang

Shih-Hang Chiu

Yung-Hsiang Chan

Chun Hsiung Tsai

Kuei-Lun Lin

Chih-Yu Hsu

Feng-Cheng Yang

Shih-Hao Lin

Xiong-Fei Yu

Shahaji B More

Cheng-Yi Peng

Kuang-Yuan Hsu

Chi On Chui

Wei-Yang Lee

Wei-Cheng Wang

Cheng-Hao Hou

Chung-Chiang Wu

Hsin-Han Tsai

Yen-Ju Chen

Wei Cheng Hsu

Mei-Yun Wang

Tung-Heng Hsieh

Chien-Hao Chen

Da-Wen Lin

Hsien-Ming Lee

Chia-Ching Lee

Peng-Soon Lim

Chih-Wei Lee

Hung-Chin Chung

Kuan-Ting Liu

Shyue-Shyh Lin

Ya-Yun Cheng

Yin-Pin Wang

Chun-Yuan Chou

Fan-Yi Hsu

Chin-Shan Hou

Tsung-Ta Tang

Chia-Yu Lu

Yu-Chia Liang

Cheng Hong Yang

An-Hung Tai

Chang-Yun Chang

Chia-Wei Hsu

Chih-Hao Yu

Shu-Han Chen

Hsiu-Hao Tsao

Chih-Hung Wang

Zoe Chen

Chun-Chih Cheng

Chang-Jhih Syu

Yao-Teng Chuang

Hsueh-Ju Chen

Fu-Kai Yang

Chen-Ming Lee

Cheng-Lung Hung

Kai-Hsuan Lee

Chien-Yuan Chen

I-Wen Wu

Chi-Chun Chen

Hsien-Chin Lin

Ming-Chi Huang

Matt Yeh

Jer-Fu Wang

Hoong Shing Wong

Jo-Chun Hung

Chi-Sheng Lai

Tsung-Da Lin

Hsing-Jui Lee

Yu-Jiun Peng

Wei-Yeh Tang

Yu-jiun Peng

Wei-Chen Hsiao

Cheng-Chieh Tu

Yen-Ta Lin

Huang-Chin Chen

Jui Fu Chueh

A method includes providing a structure having a first stack of nanostructures spaced vertically one from another and a second stack of nanostructures spaced vertically one from another, forming a dielectric layer wrapping around each of the nanostructures in the first and second stacks, depositing an n-type work function layer on the dielectric layer and a p-type work function layer on the n-type work function layer and over the first and second stacks. The n-type work function layer wraps around each of the nanostructures in the first stack. The p-type work function layer wraps around each of the nanostructures in the second stack. The method also includes forming an electrode layer on the p-type work function layer and over the first and second stacks.

Metal gates for multi-gate semiconductor devices and method thereof

A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.

Methods for doping high-K metal gates for tuning threshold voltages

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece comprising a first channel member directly over a first region of a substrate and a second channel member directly over the first channel member, the first channel member being vertically spaced apart from the second channel member, conformally forming a dielectric layer over the workpiece, conformally depositing a dipole material layer over the dielectric layer, after the depositing of the dipole material layer, performing a thermal treatment process to the workpiece, after the performing of the thermal treatment process, selectively removing the dipole material layer, and forming a gate electrode layer over the dielectric layer.

P-type semiconductor devices with different threshold voltages and methods of forming the same

In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

Structure having gate spacers with projecting portions extending into a gate dielectric

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

Post gate dielectric processing for semiconductor device fabrication

In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode formed over a channel region, a first gate dielectric layer is formed over the channel region in the gate space, a second gate dielectric layer is formed over the first gate dielectric layer, one or more conductive layers is formed on the second gate dielectric layer, the second gate dielectric layer and the one or more conductive layers are recessed, an annealing operation is performed to diffuse an element of the second gate dielectric layer into the first gate dielectric layer, and one or more metal layers are formed in the gate space.

Method of manufacturing semiconductor devices and semiconductor devices

A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.

Forming low-resistance capping layer over metal gate electrode

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, an n-type work function layer embedded in the gate dielectric layer, a dielectric capping layer embedded in the n-type work function layer, and a p-type work function layer embedded in the dielectric capping layer. A top surface of the gate structure exposes the n-type work function layer, the dielectric capping layer, and the p-type work function layer. The semiconductor structure also includes a first metal cap on the n-type work function layer and a second metal cap on the p-type work function layer. The first metal cap is spaced apart from the second metal cap. without formed on the dielectric capping layer.

Metal caps for gate structures

A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.

Device providing multiple threshold voltages and methods of making the same

A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.

Semiconductor device with non-conformal gate dielectric layers

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming an n-type work function layer in a gate trench in a gate structure, wherein the n-type work function layer is formed around first channel layers in a p-type gate region and around second channel layers in an n-type gate region, forming a first metal fill layer in a first gate trench over the n-type work function layer in the p-type gate region and in a second gate trench over the n-type work function layer in the n-type gate region, removing the first metal fill layer from the p-type gate region, removing the n-type work function layer from the p-type gate region, forming a p-type work function layer in the first gate trench of the p-type gate region, and forming a second metal fill layer in the first gate trench of the p-type gate region.

Metal gate for gate-all-around devices and methods for forming the same

In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.

Semiconductor device and method

A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.

Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same

A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Semiconductor device and method of manufacture

A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.

Semiconductor device structure and methods of forming the same

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Hsinchu, Taiwan

Jian-Hao Chen