Chartered Semiconductor Manufacturing Ltd (corporation)

Agency for Science, Technology and Research

Jian Guo Ma

Kiat Seng Yeo

Manh Anh Do

Kok Wai Johnny Chew

Hai Peng Tan

Kiat-Seng Yeo

Johnny Kok Wai Chew

Kok Lim Chan

Kok-Wai Chew

Manh-Anh Do

Chun Qi Geng

In an embodiment, a front-end transceiver may be provided. The front-end transceiver may include a receiver path, including a first receiver frequency converter configured to convert a received signal with a receiver frequency into a first receiver intermediate signal with a first receiver intermediate frequency; and a receiver direct conversion stage coupled to the first receiver frequency converter so as to receive the first receiver intermediate signal. The front-end transceiver may further include an oscillator signal generator respectively coupled to the first receiver frequency converter and to the receiver direct conversion stage so as to provide a first oscillator signal with a first oscillator frequency to the first receiver frequency converter and a first stabilizing signal with a first stabilizing frequency to the receiver direct conversion stage; wherein the oscillator signal generator may be configured so that the first oscillator frequency of the first oscillator signal may be selected such that any integer multiple of the first oscillator frequency of the first oscillator signal may be different from any integer multiple of the receiver frequency of the received signal. The front-end transceiver may also include a transmitter path.

Front-end transceiver

A new structure and method is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of a helix coil design having upper level and lower level conductors further having an axis whereby the axis of the helix coil of the inductor is parallel to the plane of the underlying substrate. Under the first embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is uniform. Under the second embodiment of the invention the height of the helix coil of the inductor of the invention is uniform while a ferromagnetic core is inserted between the upper and the lower level conductors of the helix coil. Under the third embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is non-uniform. Under the fourth embodiment of the invention the height of the helix coil of the inductor of the invention is non-uniform while a ferromagnetic core is inserted between the upper and the lower level conductors of the helix coil.

Integrated helix coil inductor on silicon

A new structure is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of spiral design and perpendicular to the plane of the underlying substrate. Conductor line width can be selected as narrow or wide, ferromagnetic material can be used to fill the spaces between the conductors of the spiral inductor. The spiral inductor of the invention can further by used in series or in series with conventional horizontal inductors.

Integrated vertical spiral inductor on semiconductor material

A new MOS varactor device is described. A bottom electrode comprises a plurality of diffusion junctions in a semiconductor substrate. The semiconductor substrate may be n-type or p-type. The diffusion junctions are arranged in a two-dimensional array. The diffusion junction may be either n-type or p-type. The diffusion junctions may be contained in a p-well or an n-well. A dielectric layer overlies the semiconductor substrate. A top electrode overlies the dielectric layer. The top electrode comprises a single polygon containing a two-dimensional array of openings therein that exposes the diffusion junctions. The top electrode preferably comprises polysilicon. An interlevel dielectric layer overlies the top electrode and the diffusion junction. The interlevel dielectric layer has a two-dimensional array of contact openings that expose the underlying diffusion junctions. A patterned metal layer overlies the interlevel dielectric layer and contacts the diffusion junctions through the contact openings.

High performance integrated varactor on silicon

In this invention a single additional capacitor is added to a tuned cascode LNA which boosts the circuit Q and the gain of the amplifier. The added capacitor creates a negative real part of the impedance which when combined with the impedance of the LC tank circuit improves both the Q and the gain of the amplifier. The capacitor does not dissipate any power, and being a passive device the capacitor does not add additional noise to the circuit. With an improved gain there is a much improved signal to noise ratio. The higher Q allows the amplifier to provide some additional bandpass and reduce image reduction requirements in subsequent amplifier stages.

Growing community of inventors

Singapore, Singapore

Jian Guo Ma