Mstar Semiconductor, Inc.

Mediatek Corporation

Jian-Feng Shiu

Chun-Chia Chen

Chao-An Chen

Eer-Wen Tyan

Yu-Chieh Hung

Kai-Fei Chang

Yao-Zhong Zhang

Ting-Kuang Wang

Yao-Tsung Hsieh

Chia-Chi Liu

A high-speed circuit with a high-voltage (HV) driver circuit. The high-speed circuit has a driver circuit and a level shifter. The driver circuit includes HV components which are operated in an HV domain. The level shifter includes low-voltage (LV) components which are operated in an LV domain. The level shifter translates signals from the LV domain to the HV domain to generate control signals for the driver circuit. The high-speed circuit may include a protection voltage generator converting a power supply voltage and a power ground voltage to generate a first direct-current bias voltage (VBP) and a second direct-current bias voltage (VBN) to bias the LV components of the level shifter. The LV components of the level shifter include input transistors and protection transistors. Gate voltages of the protection transistors may be tied to VBP or VBN.

High speed circuit with driver circuit

A receiver includes a bias current source, a comparator and an output circuit. The bias current source is powered by a first voltage source, and generates a bias current according to a second voltage source. The first voltage source is higher than the second voltage source. The comparator, coupled to the bias current source, compares two input signals to generate a comparison signal according to the bias current. The output circuit is powered by the second voltage source, and generates an output signal according to the comparison signal. The output signal and the second voltage source belong to the same power domain.

Receiver and method for controller receiver

An LDO with high efficiency receives an input voltage from an input power line and outputs an output voltage at an output power line. The LDO includes a first active device, a second active device, an operational amplifier and a protection circuit. The first and second active devices are connected in series between the input and output power lines via a connecting node. The operational amplifier controls the second active device according to the output voltage and a core power voltage of a core power line to cause the output voltage to stabilize at a target voltage value. The protection circuit is connected to the input and output power lines, the connecting node and a control node of the first active device, and controls a voltage of the connecting node and the control node of the first active device according to the input and output voltages.

LDO with high power conversion efficiency

A signal transmission method suitable for DDR for driving a connecting pad includes a level shifting circuit including up and down level shifters, a buffer circuit including up and down buffer units, and an output circuit. The level shifting circuit, disposed between a DDR operating voltage and a ground voltage, receives an input signal in a first operating voltage equal to the ground voltage and a second operating voltage smaller than the DDR operating voltage. The up buffer unit is disposed between the DDR operating voltage and a first reference voltage, and the down buffer unit is disposed between the ground voltage and a second reference voltage equal to the second operating voltage. The up and down level shifters adopt IO devices, and other components adopt core devices. The first reference voltage is a difference between the DDR operating voltage and the second reference voltage.

Signal transmission circuit suitable for DDR

A signal receiver includes a current source providing a current having a current value, a pair of active input devices, and a pair of resistors. Each active input device includes a control node, a first conduction node, and a second conduction node. One of the control nodes receives an input signal. The first conduction nodes are connected to each other and receive the current. One of the second conduction nodes serves as an output node. The active input devices output an output signal to a core circuit according to the current and the input signal. Each resistor has a resistance value. A target voltage value is determined according to the resistance value and the current value, such that a voltage swing of the output signal is limited within the target voltage value, and an operating voltage of the core circuit is substantially equal to the target voltage value.

Signal receiver

A ball grid array formed on a printed circuit board is provided. The ball grid array includes a first bailout module and a second bailout module. The first bailout module includes a plurality of first solder balls arranged as an array. Two of the first solder balls are grounded, and remaining of the first solder balls are disposed within a shielding area defined by the two grounded first balls. Two among the second solder balls are grounded, and remaining of the second solder balls are disposed within a shielding area of the two grounded second balls. The first and second bailout modules deploy substantially a same bailout arrangement, which is associated with relative positions of the two grounded solder balls and the remaining solder balls that are not grounded in each bailout module.

Growing community of inventors

Zhubei, Taiwan

Jian-Feng Shiu