Sandisk Corporation

Sandisk Technologies Inc.

Kabushiki Kaisha Toshiba

Advanced Micro Devices Corporation

Other

Alibaba Group Holding Limited

Freescale Semiconductor,inc.

Globalfoundries Inc.

Motorola Corporation

Toshiba Memory Corporation

Cadence Design Systems, Inc.

Eli Lilly and Company

Kioxia Corporation

Jds Uniphase Corporation

Nanosys, Inc.

Jian Feng Chen

Yan Li

Tomoharu Tanaka

Jeffrey W Lutze

Yingda Dong

Jun Wan

Gautam Ashok Dusija

Khandker N Quader

Yupin K Fong

Masaaki Higashitani

Raul-Adrian Cernea

Seungpil Lee

Chris Nga Yee Avila

Johann Alsmeier

Chris Avila

Man Lung Mui

Jiahui Yuan

Lee Edward Cleveland

Yuan Tang

Ming Qu

Jianmin Huang

Grishma Shah

Tien-Chien Kuo

Mrinal Kochar

Chi-Ming Wang

Loc Tu

Sergey Anatolievich Gorobets

Daniel C Guterman

Gerrit Jan Hemink

Jing-Jong J Pan

Steven Theodore Sprouse

Alon Marcu

Abhijeet Manohar

James F Buller

Akif Sultan

Liang Han

Raghuveer S Makala

Deepanshu Dutta

Nian Niles Yang

Yanli Zhang

Bich-Yen Nguyen

Dana Lee

Mark W Michael

Ching-Huang Lu

George Samachisa

Mariam G Sadaka

Scott D Luning

Yao-Sheng Lee

Senaka Kanakamedala

Ken Oowada

Shane Charles Hollmer

Voon-Yew Thean

Wei Zhao

David K Liu

Raul Adrian Cernea

Michael D Turner

Da Zhang

Geoffrey Steven Gongwer

Jixin Yu

James Juen Hsu

Wei Zhang

Ying Di Zhang

James K Kai

J Wallace Parce

Peter Rabkin

Erik C Scher

Henry Chin

Michael Allen Van Buskirk

Henry Chien

Paul J Steffan

Bing Wang

Carlos J Gonzalez

Carl Thomas Wittwer

Douglas J Lee

William P Freeman

Aaron Lee

Liang Pang

Jason T Hartlove

Robert E Wilson

Jeffery A Whiteford

Tab Allen Stephens

Hsingya Arthur Wang

Mihai A Buretea

Andrew C Lin

Ming Sang Kwan

Paul Grudowski

Christian Justus Ippen

Itai Dror

Chun Sum Yeung

Rajeev Nagabhirava

Zhengyi Zhang

Venkat Kolagunta

Jiangao Song

Ernest Lee

Jian Chen

Bikas Maiti

Charles Hotz

Zhenyu Lu

Stanley Michael Filipiak

Donald R James

Quantum dots and methods of making quantum dots are described. A method begins with forming quantum dots having a core-shell structure with a plurality of ligands on the shell structure. The method includes exchanging the plurality of ligands with a plurality of second ligands. The plurality of second ligands have a weaker binding affinity to the shell structure than the plurality of first ligands. The plurality of second ligands are then exchanged with hydrolyzed alkoxysilane to form a monolayer of hydrolyzed alkoxysilane on a surface of the shell structure. The method includes forming a barrier layer around the shell structure by using the hydrolyzed alkoxysilane as a nucleation center.

Quantum dot encapsulation techniques

This application is directed to transferring data over a data link coupled between two electronic devices. The data link includes a retimer having a full data path and a bit level data path that are coupled in parallel. The data link is initiated with the full data path and a first sequence of data packets is transferred via the full data path in accordance with a low data rate setting. While transferring the first sequence of data packets, the first sequence of data packets is manipulated in the full data path to establish a connection of the data link, and in response to establishing the connection of the data link, the data link is switched from the full data path to the bit level data path.

High speed data links with low-latency retimer

An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.

Non-volatile memory with memory array between circuits

The present disclosure relates to a unified memory apparatus having a unified storage medium and one or more processing units. The unified memory apparatus can include a first storage module having a first plurality of storage cells, and a second storage module having a second plurality of storage cells, each of the first and second plurality of storage cells configured to store data and to be identified by a unique cell identifier. The one or more processing units are in communication with the unified storage medium and the processing units are configured to receive a first input data from one of the first plurality of storage cells, receive a second input data from one of the second plurality of storage cells, and generate an output data based on the first and second input data.

Unified memory organization for neural network processors

The present disclosure provides an apparatus for analyzing trace information. The apparatus includes one or more storage devices that store a set of instructions, and one or more processors. The one or more processors are configured to execute the set of instructions to cause the apparatus to: obtain, from servers, processor instruction traces corresponding to workloads performed by the servers; generate address traces based on the processor instruction traces; and perform a workload analysis in accordance with the address traces to model resource demands of the workloads.

Apparatus, method, and non-transitory computer-readable medium for analyzing trace information

One embodiment provides a system and method for facilitating error-correction protection in a storage device. In response to a write request, the system organizes a block of data in a two-dimensional (2D) array, forms a plurality of first-dimension sub-blocks by dividing the 2D array along a first dimension, and forms a plurality of second-dimension sub-blocks by dividing the 2D array along a second dimension. In response to determining that second-dimension error correction code (ECC) encoding is enabled, the system performs second-dimension ECC encoding on the second-dimension sub-blocks to generate a set of second-dimension ECC bits and performs first-dimension ECC encoding on the first-dimension sub-blocks and the second-dimension ECC bits to generate a set of first-dimension ECC bits. The system writes the data block along with the second-dimension ECC bits and the first-dimension ECC bits to the storage device. The data block and the second-dimension ECC bits are mapped to separate physical addresses in the storage device.

Memory-mapped two-dimensional error correction code for multi-bit error tolerance in DRAM

The present disclosure provides an on-chip communication system for neural network processors, a processing device, and a method for operating on an on-chip communication system. The system can include a cluster manager configured to generate a global signal, and a plurality of tile units in a tile array coupled with the cluster manager, each including two connectors and a node connected between the two connectors.

On-chip communication system for neural network processors

A system is provided for performing error correction in memory. During operation, the system can receive a memory access request from a host processor. The system can then compare a memory address specified in the memory access request with a set of entries in an error correction code (ECC) mapping table. In response to the system determining that the memory address corresponds to at least one entry in the ECC mapping table, the system may determine, based on value in the counter field, whether the memory address belongs to a first portion or a second portion of the address range specified in the ECC mapping table entry. The system can then select a current ECC mode when the memory address belongs to the first portion; and select a previous ECC mode when the memory address belongs to the second portion. The system may then process the memory access request based on the selected ECC mode.

System and method for facilitating elastic error correction code in memory

A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell

A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.

Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip

The present disclosure provides a system for monitoring I/O traffic. The system includes a memory storing information, a device, and a translation lookaside buffer (TLB). The device is configured to send a request for accessing information from the memory. The TLB includes a counter register file having counter registers, and entries having corresponding counter ID fields. The TLB is configured to receive a source identifier of the device and a virtual address associated with the request from the device, select an entry of the entries using the source identifier and the virtual address, select a counter register from the counter registers in accordance with information stored in the counter ID field of the selected entry, and update a value of the selected counter register in accordance with data transferred in association with the request.

System and method for monitoring per virtual machine I/O

The present disclosure provides a processor providing a memory architecture having M-number of processing elements each having at least N-number of processing units and a local memory. The processor comprises a first processing element of the M-number of processing elements comprising a first set of N-number of processing units configured to perform a computing operation, and a first local memory configured to store data utilized by the N-number of processing units. The processor further comprises a data hub configured to receive data from the M-number of processing elements and to provide shared data to each processing element of the M-number of processing elements.

Centralized-distributed mixed organization of shared memory for neural network processing

Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

Three-dimensional memory device having bonding structures connected to bit lines and methods of making the same

Growing community of inventors

Hayward, CA, United States of America

Jian Feng Chen