United Microelectronics Corp.

Jian-Cheng Chen

Yu-Ping Wang

Yu-Ruei Chen

Chung-Liang Chu

Chen-Hua Tsai

Yao-Jen Fan

Heng-Kun Chen

Hsiang Yang

Chin-Yueh Tsai

Chih-Wei Hsu

Jui-Yun Chang

I-Jen Kao

A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Magnetoresistive random access memory having a ring of magnetic tunneling junction region surrounding an array region

A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, wherein the ring of MTJ region comprises a first MTJ, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, each of the metal interconnect patterns includes a first metal interconnection connected to the first MTJ directly.

A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region comprises an octagon and the ring of MTJ region includes a first MTJ region and a second MTJ region extending along a first direction, a third MTJ region and a fourth MTJ region extending along a second direction, a fifth MTJ region and a sixth MTJ region extending along a third direction, and a seventh MTJ region and an eighth MTJ region extending along a fourth direction.

A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Magnetoresistive random access memory

A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having second sizes, and a plurality of bar-like third dummy patterns having varied third sizes. The pattern densities are smartly equalized by positioning the second dummy patterns.

Dummy patterns

A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.

Dummy patterns and method for generating dummy patterns

A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.

The invention is directed to a method for checking a die seal ring on a layout. The method comprises steps of receiving a digital database of a layout corresponding to at least a device with a text information corresponding to the layout. Tape-out information corresponding to the layout is received. A checking process is performed according to the digital database of the layout and the tape-out information and, meanwhile, a mask design procedure for designing a mask pattern corresponding to the layout is performed by using the digital database of the layout, the text information and the tape-out information. A result of the checking process is recorded in an inspection table corresponding to the layout.

Growing community of inventors

Taipei, Taiwan

Jian-Cheng Chen