United Microelectronics Corp.

Jian-Bin Shiu

Tung-Sheng Lee

Chin-Wen Huang

Ching-Ming Lee

Wen-Zheng Yu

A structure of a conductive pad is provided. The structure includes a first conductive layer. A first dielectric layer covers the first conductive layer. A first contact hole is disposed within the first dielectric layer. A second conductive layer fills in the first conductive hole and extends from the first conductive hole to a top surface of the first dielectric layer so that the second conductive layer forms a step profile. A second dielectric layer covers the first dielectric layer and the second conductive layer. A third conductive layer contacts and covers the step profile.

Conductive pad structure and method of fabricating the same

A semiconductor sensor device is disclosed. The semiconductor sensor device includes a plurality of pixels and a phase grating structure. The phase grating structure has periodically arranged patterns and is disposed on the pixels.

Semiconductor sensor device

A semiconductor device is disclosed. The semiconductor device includes: a substrate having a die region and a scribe line region defined thereon; and a bonding pad on the die region of the substrate and overlapping the scribe line region.

Semiconductor device and method for fabricating the same

A monitoring method of a semiconductor process includes the following steps. A semiconductor substrate is provided, and a test structure is formed thereon. The method of forming the test structure includes the following steps. A first doped region and a second doped region are formed in the semiconductor substrate, and an insulating layer is formed on the semiconductor substrate. Subsequently, a conductive layer is directly formed on the insulating layer to complete the formation of the test structure, in which the conductive layer in a floating state partially overlaps the first doped region and partially overlaps the second doped region. Then, a voltage signal is applied to the test structure and the breakdown voltage (Vbd) between the first doped region and the second doped region is measured.

Test structure for semiconductor process and method for monitoring semiconductor process

A phase grating includes a substrate and a first dielectric layer. The first dielectric layer is disposed on the substrate and includes a column and a plurality of rings. The top sides of the column and the top sides of the rings align with one another to form a flat plane. The column and the rings are concentric.

Phase grating with three-dimensional configuration

A bipolar junction transistor (BJT) integrated with a PIP capacitor includes a substrate including a bipolar junction transistor region and a PIP capacitor region, a bipolar junction transistor disposed in the bipolar junction transistor region and extending an isolation layer to the PIP capacitor region and a base poly layer disposed on the isolation layer, and a PIP capacitor disposed in the PIP capacitor region and including a lower poly layer, the isolation layer and the base poly layer to selectively form a PIP capacitor.

Bipolar junction transistor integrated with PIP capacitor and method for making the same

A method for forming a phase grating is disclosed. First, a substrate is provided. Second, a first dielectric layer with a tapered recess or bulge is formed on the substrate. Later, a second dielectric layer is formed to fill the tapered recess and to cover the first dielectric layer. Afterwards, the second dielectric layer is selectively etched to form the phase grating. The phase grating includes a column and multiple rings. The column and multiple rings are concentric and the multiple rings are disposed on the tapered side so that the height of each ring is different.

Method for forming phase grating

A passivation structure and fabricating method thereof includes providing a chip having a main die region and a scribe line region defined thereon and a plurality of metal pads respectively positioned in the main die region and the scribe line region, forming a first patterned passivation layer having a plurality of first openings and second openings respectively exposing the metal pads in the main die region and the scribe line region on the chip, and forming a second patterned passivation layer filling the first openings in the scribe line region and having a plurality of third openings corresponding to the first openings thus exposing the metal pads in the main die region.

Passivation structure and fabricating method thereof

A phase grating image-sensing device. The device includes a plurality of photodiodes, a smoothing layer, a color filter layer and a plurality of phase gratings. The photodiodes are formed on a substrate and isolated from each other by isolation structures. The smoothing layer covers the photodiodes and the isolation structures. The color filter layer is embedded within the smoothing layer forming a sandwich structure with the smoothing layer. The phase gratings are formed over the smoothing layer positioned at corresponding locations above isolation structures. The phase grating layers produce a constructive interference of light passing through the smoothing layer.

Phase grating image sensing device and method of manufacture

A method of manufacturing a phase grating image sensor is disclosed. The method uses conventional photolithography and etching methods to form a plurality of phase grating lenses into the conventional flattening layer on which the conventional micro-lens is formed. The invention thus utilizes phase gratings to replace the conventional micro-lens.

Growing community of inventors

Hsinchu, Taiwan

Jian-Bin Shiu