Silergy Semiconductor Technology (hangzhou) Ltd

Jiaming Ye

Xiaochun Tan

Junli Shentu

Chen Zhao

Chiqing Fang

A package structure of a power converter, can include: a die pad; an insulation adhesive layer and a conductive adhesive layer on the die pad; a control circuit die on the insulation adhesive layer, where the insulation adhesive layer comprises a first insulation adhesive layer on a back surface of the control circuit die, and a second insulation adhesive on a surface of the die pad, where the first insulation adhesive layer is connected to the second insulation adhesive layer; and a power device die on the conductive adhesive layer, where the insulation adhesive layer is separated from the conductive adhesive layer.

Package structure for power converter and manufacture method thereof

A die attachment structure can include: a base; a die located above a first surface of the base; a first adhesive layer located on a back surface of the die, wherein the die is pasted on the first surface of the base at least by the first adhesive layer; and a second adhesive layer at least partially covering the sidewalls of the die.

Die attachment structure and method for manufacturing the same

A package structure applied to power converters can include: a first die having a first power transistor and a first control and drive circuit; a second die having a second power transistor; a connection device configured to couple the first and second power transistors in series between a high-level pin and a low-level pin of a lead frame of the package structure; and where a common node of the first and second power transistors can be coupled to an output pin of the lead frame through a metal connection structure with a low interconnection resistance.

Package structure applied to power converter

The present disclosure relates to a chip package structure and a method for forming a chip package. A package unit is formed from the chip and an encapsulant surrounding the chip to have an increased area. A redistribution layer is formed on the package unit to draw out to and redistribute input/output terminals on a surface of the chip. The redistribution layer is then electrically coupled to a leadframe or a printed circuit board by external and electrical connectors. The method and the package structure are suitable for providing a chip package having input/output terminals with high density, reducing package cost, and improving package reliability.

Chip package structure and method for forming chip package

In one embodiment, an IC package assembly for a switching regulator, can include: a power switch chip including a control electrode and a first electrode on an obverse side and a second electrode on a reverse side, where the second electrode is configured as a switching terminal of a switching regulator; a control chip including a driving electrode and a plurality of input and output electrodes on the obverse side; and a leadframe including an extension pin, a substrate, and a plurality of discrete pins, where the extension pin is formed integrally with the substrate, and where the reverse side of the power switch chip is arranged on the substrate of the leadframe by a conductive material to electrically connect the second electrode to the substrate.

Integrated package assembly for switching regulator

A package structure and a method for manufacturing the same are disclosed. The package structure includes a first plastic body which covers a first light sensor and a light emitter, and a second plastic body which is made of infrared cutoff materials and fills inner pins of a lead frame or is formed below the lead frame. A trench is formed in the first plastic body so that a light-blocking layer is located on a side surface of the first plastic body. The second plastic body and the light-blocking layer are used to avoid influence of infrared light on a first light sensor.

Package structure of light emitter and light sensor with light-blocking layer and method for manufacturing the same

A package assembly and a method for manufacturing the same are disclosed. The package assembly includes a leadframe having at least two groups of leads and a plurality of electronic devices arranged in at least two levels. Each group of leads is electrically coupled to a respective level of electronic devices. The package assembly further includes an interconnect for coupling one or more leads of one group of leads to one or more leads of another group of leads. The package assembly results in increased packaging density, less usage of bonding wires in the package assembly, improves reliability, and prevents possible interference.

Package assembly having interconnect for stacked electronic devices and method for manufacturing the same

A package assembly can include: (i) a plurality of electrical components stacked on at least two layers; (ii) a lead frame connected to the electrical components by solder interconnection; (iii) an encapsulating compound overlapping a portion of the lead frame and the electrical components to expose portions of leads of the lead frame from the encapsulating compound; and (iv) a heat sink having a first portion arranged between two of the plurality of electrical components, where the heat sink is configured to provide a common heat dissipation path for the electrical components.

Package assembly and method for manufacturing the same

The present disclosure relates to a chip package method and a package assembly. A metal plate is micro-etched to form trenches having a predetermined depth. A metallic conductor is formed as a leadframe by filling the trenches with a material having relatively small adhesion with the metal plate. In such manner, the metal plate can be peeled off from a package body after the chip is electrically coupled to the metallic conductor and encapsulated by a molding process. A bottom of the metallic conductor is exposed from the package body. A chip package is thus completed. It simplifies a manufacture process for forming a chip package, reduces manufacture cost, and increases reliability of the chip package.

Chip package method and package assembly

A leadframe, a package assembly and methods for manufacturing the same are disclosed. A plurality of electronic devices are stacked in a plurality of levels in the package assembly. The leadframe includes a plurality of leads having interconnect areas. The plurality of leads are grouped so that the interconnect areas of each group of leads have a height corresponding to one level of electronic devices. In the package assembly, the interconnect areas of each group of leads are soldered to one level of electronic devices. The leadframe and the package assembly result in increased packaging density, less usage of bonding wires in the package assembly, and improve reliability. The method for manufacturing the package assembly reduces adverse effects of a reflow process on properties of the electronic devices, and thus further improves reliability of the package assembly.

Multi-level leadframe with interconnect areas for soldering conductive bumps, multi-level package assembly and method for manufacturing the same

In one embodiment, a chip package assembly can include: a first substrate at a bottom layer, the first substrate having a first surface and a second surface opposite to the first surface, where the second surface is provided with a first group of inner leads; at least one chip layer above the first group of inner leads, where each of the chip layers comprises a third surface and a fourth surface opposite to the third surface, where electrodes on the third surface that that lie at the lowest level are electrically coupled to the first group of inner leads through a first connector; and a second substrate above the fourth surface on the topmost layer and having a fifth surface, and where the fifth surface is provided with a second group of inner leads electrically coupled to the electrodes on the fourth surface on the topmost layer.

Growing community of inventors

Hangzhou, China

Jiaming Ye