Reed Semiconductor Corp.

Jialun Du

Jiwei Fan

Hal Chen

Yingqian Ma

Jingyuan Chen

Wenkai Wu

Weidong Zhu

A frequency lock loop for a constant switching frequency of DC-DC converter, wherein the frequency lock loop includes a modulation circuit to generate a modulation signal in response to an input signal of the DC-DC converter and a frequency signal. Wherein a timer of the DC-DC converter generates a timing signal in response to the input signal, and wherein the frequency signal is a function of the timing signal.

Frequency lock loop for constant switching frequency of DC-DC converters

A buck converter with an asymmetric threshold voltage of its gate drive circuit design for improving power efficiency while keeping the gate drive design simple.

Buck converter system with an asymmetric threshold voltage gate drive circuit design

A deadtime control scheme for improving buck converter light load efficiency.

Deadtime control scheme for improving buck converter light load efficiency

A ramp generator for a constant on-time DC-DC converter, wherein the ramp generator is configured to reduce DC offset and smooth transitions between conduction modes. The ramp voltage generator includes a common voltage generator suitable for generating a common voltage; a first ramp voltage generation block suitable for generating a first ramp voltage responsive to a first switching signal and a control signal, wherein the first switching signal resets one or more valley points of the first ramp voltage to one or more valley points of the common voltage; and a second ramp voltage generation block suitable for generating a second ramp voltage responsive to a second switching signal, the first ramp voltage, and the control signal.

Growing community of inventors

Dublin, OH, United States of America

Jialun Du