Tsinghua University

Jialong Liu

Huazhong Yang

Chen Jiang

Xueqing Li

Wenjun Tang

Yongpan Liu

Yilun Zhong

Weihang Long

The present disclosure relates to a sensing-memory-computing synergy device, chip and electronic device. The said device comprises: at least one sensing-memory-computing synergy cell, wherein each sensing-memory-computing synergy cell comprises K sensing elements, where the first end of each sensing element is connected to wordline, the second end of each sensing element is connected to bitline, the sensing element can sense changes in external inputs, and K is an integer greater than or equal to zero; a control module which controls the voltages of each wordline and bitline so that the sensing-memory-computing synergy cell can perform desired operations, and sense the voltage or current on bitlines to obtain the operation results. The present embodiment of the disclosure implements the sensing-memory-computing synergy cell by sensing elements, which combines sensing and in-memory computing. The sensing elements gather sensor data from external inputs, and the sensing-memory-computing synergy operation is performed by controlling the voltages on wordlines and bitlines. The present embodiment of the disclosure enables the in-situ sensing, memory and computing functions in a device with decreased wiring and control complexity, which lowers the computing latency and improves robustness and energy efficiency.

Devices, chips, and electronic equipment for sensing-memory-computing synergy

A computing-in-memory array, chip and electronic device includes a computing-in-memory array including at least one computing-in-memory cell having a first switch, a second switch, a third switch, a fourth switch, a coupling capacitor, a first bitline, a second bitline, a third bitline, a first wordline, a second wordline and a third wordline; a control module connected to the computing-in-memory array, which controls the voltages of each wordline and bitline to read and write data through the computing-in-memory array, or to perform computing-in-memory operations. By arranging the first switch, the second switch, the third switch, and the fourth switch in a differential form, and determining the stored value by the difference of the voltage between the two ports of the second switch and the third switch, the present embodiment of the disclosure can implement computing-in-memory operations with high accuracy, low circuit complexity, high reliability, and high energy efficiency. For memory function, the computing-in-memory device has a long data retention time and low data refresh overhead.

Devices, chips, and electronic equipment for computing-in-memory

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Beijing, China

Jialong Liu