Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Jialei Liu

Bo Li

Yonggen He

Lin Liu

Huanxin Liu

Peng Yang

Qingsong Wei

Ruizhi Tang

Haojun Huang

Chaowei Li

Jinyu Fu

A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a substrate; forming a dummy gate structure including a dummy gate dielectric layer, an initial dummy gate electrode layer, and a first sidewall spacer; forming an isolation layer having a surface lower than or coplanar with the dummy gate structure; forming a dummy gate electrode layer having a surface lower than the isolation layer, and forming a first opening to expose a portion of the first sidewall spacer; forming a modified sidewall spacer from the exposed first sidewall spacer; forming a second opening by removing the dummy gate electrode layer; forming a third opening by removing the dummy gate dielectric layer and the modified sidewall spacer, where top of the third opening has a size larger than bottom of the third opening; and forming a gate structure in the third opening.

Semiconductor structure and fabrication method thereof

A method for forming a semiconductor device includes providing a semiconductor substrate including a PMOS region and an NMOS region. A spacer material layer is deposited. Then, a first photo masking and etch process is used to form first sidewall spacers on the sidewalls of the gate structures in the NMOS region. A sacrificial surface layer is formed. Next, a second photo masking and etch process is used to form second sidewall spacers on the sidewalls of the gate structures in the PMOS region. After the second photoresist layer is removed, with the sacrificial layer masking the NMOS region, stress layers are formed in source/drain regions in the PMOS region, and a cover layer is formed on the stress layers. The method further includes removing the sacrificial material layer, the first sidewall spacers, and the second sidewall spacer.

Method for reducing loss of silicon cap layer over SiGe source/drain in a CMOS device

A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate; and forming gate structures on a surface of the semiconductor substrate. The method also includes forming sidewall spacers around the gate structures; and forming a protection layer on the sidewall spacers. Further, the method includes forming sigma shape trenches in the semiconductor substrate at sides of the gate structures; and forming SiGe structures with a surface protruding from the surface of the semiconductor substrate in the sigma shape trenches. Further, the method also includes removing the sidewall spacers and a portion of the protection layer; and forming lightly doped drain regions in the semiconductor substrate at both sides of the gate structures.

PMOS transistors and fabrication methods thereof

A method of fabricating semiconductor device includes forming a recess having a substantially rectangular section and forming an oxide layer on sidewalls and an oxide layer on a bottom of the recess by anisotropic oxidation, wherein the oxide layer on the sidewalls is thinner than the oxide layer on the bottom of recess. The method further includes completely removing the oxide layer on the sidewalls and partially removing the oxide layer on the bottom of the recess. The method also includes performing an orientation selective wet etching on the recess using a remaining oxide layer of the recess as a stop layer to shape the sidewalls into a &#x3a3; shaped section. The method includes removing the remaining oxide layer using an isotropic wet etching.

Method for fabricating a semiconductor device

Growing community of inventors

Shanghai, China

Jialei Liu