Chinese Academy of Sciences

Jiajun Luo

Zhengsheng Han

Jianhui Bu

Jinshun Bi

Tianchun Ye

Fazhan Zhao

Shuzhen Li

Yinxue Lv

The present disclosure discloses a power device including at least one vacuum packaged unit structure. The unit structure comprises a silicon substrate () and an emitter (), a light modulator () and a collector () formed on the silicon substrate (). On the one hand, the unified silicon-based process is compatible with the existing commercial process, so that it is easy for integration, simple for manufacture, and low in cost; on the other hand, the light modulator () is introduced and formed on the silicon substrate by a silicon-based process, which enhances field emission efficiency of the emitter (), offsets the inconsistency of distances between the tips of the emitters () and the collector () caused by unevenness of the emitters, and increases the process redundancy of the cold cathode emitter.

Power device and fabrication method thereof

The invention discloses an STI stress effect modeling method and device of an MOS device, and belongs to the technical field of parameter extraction modeling of devices. The method comprises the following steps: introducing the influence of temperature parameters on the STI stress effect of the MOS device, so as to form a function showing that the STI stress effect of the MOS device changes along with the temperature parameters; extracting the model parameter Modelof the MOS device at normal temperature; on the basis of the Model, extracting the parameter Modelthat the STI stress affects the properties of the MOS device at normal temperature; and on the basis of the Model, extracting fitting parameters of the MOS device in the function so as to acquire final model parameters. The device comprises a first module, a second module, a third module and a fourth module. By establishing the function showing that the STI stress effect of the MOS device changes along with the temperature parameters, the influence of the temperature on the STI stress effect of the MOS device can be accurately described, so that the extracted model parameters are more accurate and reliable.

STI stress effect modeling method and device of an MOS device

The present invention provides a SOI MOS device modeling method. The SOI MOS device is one having a source-drain injection not reaching the bottom. The method comprises: a) establishing an overall model comprising a primary MOS device model simulating an SOI MOS device having the source-drain injection reaching the bottom, a source body PN junction bottom capacitance model simulating a source body PN junction bottom capacitance, and a drain body PN junction bottom capacitance model simulating a drain body PN junction bottom capacitance; and b) extracting parameters respectively for the primary MOS device model, the source body PN junction bottom capacitance model, and the drain body PN junction bottom capacitance model in the overall model. In the prior art, the source body junction bottom capacitance and the drain body junction bottom capacitance in the SOI MOS device having a source-drain injection not reaching the bottom affect the performances of the device. The modeling method of the present invention takes the effect into consideration, improves model precision, and can be effectively used for the simulation design of a device.

SOI MOS device modeling method

A method for improving anti-radiation performance of SOI structure that includes implementing particle implantations of high-energy neutrons, protons and &#x3b3;-rays to a buried oxide layer of an SOI structure, and then performing annealing process. The high-energy particle implantation introduces displacement damage to the buried oxide layer of the SOI structure.

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Beijing, China

Jiajun Luo