Qualcomm Incorporated

Jiajin Tu

Suresh Kumar Venkumahanti

Erich Plondke

Phillip M Jones

Christopher E Koob

Lucian Codrescu

Brian Robert Mestan

Lin Wang

Stephen Robert Shannon

Daisy T Palal

A translation lookaside buffer (TLB) stores translation entries. The translation entries include a virtual address, a physical address and a memory local/not-local flag. When a processor is in a low power/local memory mode a virtual address is received. A matching translation entry has a local/not-local flag. Upon the local/not-local flag indicating the physical address of the matching translation entry being outside the local memory, an out-of-access-range memory access exception is generated.

Selective translation lookaside buffer search and page fault

A method includes receiving an instruction to be executed by a processor. The method further includes performing a lookup in a page crossing buffer that includes one or more entries to determine if the instruction has an entry in the page crossing buffer. Each of the entries includes a physical address. The method further includes, when the page crossing buffer has the entry in the page crossing buffer, retrieving a particular physical address from the entry in the page crossing buffer.

Speculative addressing using a virtual address-to-physical address page crossing buffer

Processor access of memory is monitored. The monitoring includes identifying the accesses being to a local memory or a non-local memory. Based on the monitoring, the processor is switched from a non-local memory access mode to a local memory access mode.

Adaptive mode translation lookaside buffer search and access fault

An example method of storing a partial target address in an instruction cache includes receiving a branch instruction. The method also includes predicting a direction of the branch instruction as being not taken. The method further includes calculating a destination address based on executing the branch instruction. The method also includes determining a partial target address using the destination address. The method further includes in response to the predicted direction of the branch instruction changing from not taken to taken, replacing an offset in an instruction cache with the partial target address.

Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process

Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.

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Jiajin Tu