Alibaba Group Holding Limited

T-head (shanghai) Semiconductor Co., Ltd.

C-sky Microsystems Co., Ltd.

Jiahui Luo

Yubo Guo

Zhijian Chen

Wenmeng Zhang

Chang Liu

Taotao Zhu

Zhesheng Luo

This disclosure provides an instruction transmitting unit, an instruction execution unit, and a related apparatus and method. The instruction transmitting unit includes: an instruction splitter adapted to split a to-be-executed vector instruction into microinstructions; a microinstruction index fetcher adapted to acquire a number-of-effective-elements index of the microinstructions resulting from the splitting based on an element range involved in the microinstructions; an index comparison subunit adapted to compare the acquired number-of-effective-elements index with a first index, where the first index is a number-of-effective-elements index of a fault-only-first microinstruction whose processing has not been completed; and a microinstruction transmission controller adapted to transmit the microinstructions resulting from the splitting to a vector execution unit for execution when the number-of-effective-elements index is less than the first index. This disclosure improves operating efficiency of subsequent vector instructions when a fault-only-first vector loading instruction is involved in chaining.

Splitting vector instructions into microinstructions for parallel execution based on index comparisons of completed microinstructions

The present invention discloses an instruction processing apparatus, comprising a first register adapted to store first source data, a second register adapted to store second source data, a third register adapted to store accumulated data, a decoder adapted to receive and decode a multiply-accumulate instruction, and an execution unit. The multiply-accumulate instruction indicates that the first register serves as a first operand, the second register serves as a second operand, the third register serves as a third operand, and a shift flag. The execution unit is coupled to the first register, the second register, the third register, and the decoder, and configured to execute the decoded multiply-accumulate instruction so as to acquire the first source data from the first register and acquire the second source data from the second register, perform a multiplication operation on the first source data and the second source data so as to obtain a multiplication result, shift the multiplication result according to the shift flag, and add the shifted multiplication result and the accumulated data in the third register so as to obtain a multiply-accumulate result. The present invention further discloses a corresponding instruction processing method, a computing system, and a system on chip.

Multiply-accumulate instruction processing method and apparatus

The present disclosure discloses an instruction processing apparatus, comprising a first vector register adapted to store a first vector to be operated on, a second vector register adapted to store a second vector to be operated on, a decoder adapted to receive and decode a data splicing instruction, and an execution unit. The data splicing instruction indicates the first vector register as a first operand, the second vector register as a second operand, a splicing indicator, and a destination. The execution unit is coupled to the first vector register, the second vector register, and the decoder, and is adapted to execute the decoded data splicing instruction, so as to acquire a first part of the first vector from the first vector register and acquire a second part of the second vector from the second vector register according to the splicing indicator, splice the acquired first part of the first vector and the acquired second part of the second vector to form a third vector, and store the third vector into the destination.

Method and apparatus for processing data splicing instruction

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Hangzhou, China

Jiahui Luo