Advanced Micro Devices Corporation

Advance Micro Devices, Inc.

Jiahua Huang

Allison Holbrook

Yue-Song He

Sunny Cherian

Jeffrey Allan Shields

Kent Kuohua Chang

John S Foster

Jean Yee-Mei Yang

Pei-Yuan Gao

Yuesong He

Anne E Sanderfer

James Chiang

Frank Mak

Aaron A Fernandes

Spacer etch trim techniques are provided. The method controllably trims a multi-film stack spacer utilizing a self-limiting etch technique. The method may use a dry etch etcher with low bias power. The dry etch process may also use other modified parameters, such as gas flows and various pressures.

Method for lateral trimming of spacers

A method and system for eliminating post etch residues is disclosed. In one method embodiment, the present invention recites disposing a surface, having post etch residues adhered thereto, proximate to an electron beam source which generates electrons. The present method embodiment then recites bombarding the post etch residues with the electrons such that the post etch residues are removed from the surface to which the post etch residues were adhered.

Method and system for eliminating post etch residues

A process for fabricating a semiconductor device, the process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes, performing an isotropic etch on the oxide-nitride-oxide layer to remove a portion of the oxide-nitride-oxide layer.

Method for selective removal of ONO layer

A method of manufacturing a semiconductor device is provided in which a tunnel dielectric layer and a gate layer are formed on a semiconductor wafer and a trench forming technique is used to define a floating gate structure. An insulator is deposited in the trench whereby the gate layer and the tunnel dielectric layer form a gate which is self-aligned to a tunnel dielectric.

Self-aligned gate semiconductor

An improved etch of thick protective topside stack films, which cover metal pads of a semiconductor device. The invention uses a downstream plasma isotropic etch to etch the topside stack film. In one embodiment, the downstream plasma isotropic etch is used to etch only part of the topside stack films. A subsequent anisotropic oxide plasma etch is used to etch the remaining topside stack film to the metal pads. In another embodiment, the downstream plasma isotropic etch is used to etch completely through the topside stack films to the metal pad. The invention allows the etching through topside stack films greater than 5 microns.

High selectivity pad etch for thick topside stacks

A silicon layer is etched using a plasma etcher equipped with an endpoint control device. CF and N are provided to the plasma etcher at lower flow rates than those typically used during fixed time etching processes. The endpoint control device monitors optical emissions from the etching chamber at a particular wavelength to detect a predetermined change in intensity. When the change in intensity is detected, the etching is terminated.

Method for amorphous silicon local interconnect etch

In the manufacture of an EPROM or EEPROM semiconductor device that includes a core region and a peripheral region, a nitride layer is formed over the core region and peripheral region, and an oxide layer is formed over the nitride layer. A layer of photoresist is provided over the oxide layer and is patterned to expose a portion of the oxide layer overlying the core region. A wet etch step is undertaken to remove the exposed portion of the oxide layer, using the patterned photoresist as a mask, and leaving exposed a portion of the nitride layer overlying the core region. After removal of the photoresist, the exposed portion of the nitride layer is etched by a wet etch step with hot phosphoric acid, using the pattered oxide layer as a mask.

Double layer hard mask process to improve oxide quality for non-volatile flash memory products

A method of manufacturing semiconductor wafers wherein a metal layer is formed on a surface of a layer of interlayer dielectric on a partially completed semiconductor wafer and if it is determined that the metal layer is faulty, the faulty metal layer is removed, the surface of the layer of interlayer dielectric is lowered below the tops of metal plugs formed in the layer of interlayer dielectric, the tops of the metal plugs are planarized to the surface of the layer of interlayer dielectric and the metal layer is reformed on the surface of the interlayer dielectric. If the metal layer is determined to be good, the metal layer is etched. If the metal etch is faulty, the metal layer is removed, the layer of interlayer dielectric is reduced to below the tops of plugs formed in the layer of interlayer dielectric, the tops of the metal plugs are planarized down to the surface of the layer of interlayer dielectric and the layer of metal is reformed.

Method to rework device with faulty metal stack layer

A method of forming floating gate to improve tunnel oxide reliability for flash memory devices. A substrate having a source, drain, and channel regions is provided. A tunnel oxide layer is formed over the substrate. A floating gate is formed over the tunnel oxide and the channel region, the floating gate being multi-layered and having a second layer sandwiched between a first layer and a third layer. The first layer of the floating gate overlying the tunnel oxide layer includes an undoped or lightly doped material. The second layer is highly-doped. The third layer is in direct contact with a dielectric layer, e.g., an oxide-nitride-oxide stack, and is made of an undoped or lightly doped material. A dielectric material is formed over the floating gate and a control gate is formed over the dielectric material.

Floating gate engineering to improve tunnel oxide reliability for flash

Tunnel oxide degradation is reduced by reducing residual photoresist material in open areas of a mask pattern. Embodiments include detecting residual photoresist in an exposed underlying region of a substrate by x-ray spectroscopy and descumming in response to detected residual photoresist.

Method for manufacturing memory devices

Apparatus for monitoring the hydrogen peroxide concentration in a sulfuric acid bath used to remove photoresist from semiconductor wafers uses the amount of bubbles in the fluid mixture to signal the addition of hydrogen peroxide. The bubbles are directly related to the hydrogen peroxide in sulfuric acid mixture. The bubbles are sensed by a light source and photoelectric sensor connected to a threshold adjustment control which controls a metering solenoid valve to add hydrogen peroxide from a reservoir to the bath when the bubbles decrease.

Growing community of inventors

San Jose, CA, United States of America

Jiahua Huang