Inspur Suzhou Intelligent Technology Co., Ltd

Suzhou Metabrain Intelligent Technology Co., Ltd.

Jiaheng Fan

Hongwei Kan

Rengang Li

Yanwei Wang

Zhixin Ren

Weifeng Gong

Mingyang Ou

A heterogeneous acceleration method, including the following steps: analyzing a received target data packet to obtain data source end identification information; when the data source end identification information does not exist in a configuration information table, customizing a data message format according to the target data packet to obtain a target data message format, or when the data source end identification information exists in the configuration information table, reading the target data message format from the configuration information table; and according to the target data message format, performing acceleration processing on the target data packet to obtain processed data, and returning the processed data to a data source end.

Heterogeneous acceleration method, apparatus and system and computer readable storage medium

An FPGA cloud platform acceleration resource allocates and coordinates accelerator card resources according to delays between a host of a user and FPGA accelerator cards deployed at various network segments. Upon an FPGA usage request of the user, allocating an FPGA accelerator card in an FPGA resource pool that has a minimum delay to the host. A cloud monitoring management platform obtains_transmission delays to a virtual machine network according to different geographic locations of various FPGA cards in the FPGA resource pool, and allocating a card having a minimum delay to each user. The cloud monitoring management platform prevents unauthorized users from accessing acceleration resources in the resource pool. The invention protects FPGA accelerator cards that are not authorized for users, and ensures that the card allocated to a user has a minimum network delay, thereby optimizing acceleration performance, and improving user experience.

FPGA cloud platform acceleration resource allocation method, and system

Disclosed are a method for data synchronization between a host side and a Field Programmable Gate Array (FPGA) accelerator, a Bidirectional Memory Synchronize Engine (DMSE), a FPGA accelerator, and a data synchronization system. The method includes: in response to detection of data migration from a host side to a preset memory space, generating second state information according to first state information in a first address space, and writing the second state information to a second address space (S); and in response to detection of the second state information in the second address space, calling Direct Memory Access (DMA) to migrate data in the preset memory space to a memory space of a FPGA accelerator, and copying the second state information to the first address space, so as to implement synchronization (S).

Method for data synchronization between host side and FPGA accelerator

Growing community of inventors

Jiangsu, China

Jiaheng Fan