Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

Jia Zhen Zheng

Lap Chan

Elgin Kiok Quek

Yelehanka Ramachandramurthy Pradeep

Yang Pan

Ravi Sundaresan

Ying Keung Leung

James Yong Meng Lee

Chew Hoe Ang

Pradeep Yelehanka

Purakh Raj Verma

Weining Li

Sanford Chu

Shao-fu Sanford Chu

Chit Hwei Ng

Eng Hua Lim

Wenhe Lin

Jian Xun Li

Daniel Yen

Tommy Lai

Mei Sheng Zhou

Randall Cher Liang Cha

Soh Yun Siah

Tze Ho Simon Chan

Chew-Hoe Ang

Randall Cha

Simon Yew-Meng Chooi

Liang Choo Hsia

Yi Liang Xu

Wei Lu

Kai Shao

Tong Qing Chen

Paul Proctor

Subramanian Balakumar

Johnny Chew

Choon Beng Sia

Zhi Yong Han

Kelvin Ong

Tian Hao Gu

Syn Kean Cheah

Dong Zhong

James Lee Yong Meng

Ying Keung

Elgin Kiok Boone Quek

Mei-Sheng Zhou

Yong Meng Lee

Yeow Kheng Lim

Yun Ling Tan

Charles Lin

Narayanan Balasubramanian

Marvin De-Dui Liao

Sia Choon Beng

Yih-Shung Lin

Shao Kai

Alex Kai Hung See

Kho Liep Chok

Eng-Hua Lim

James Yongmeng Lee

Yong Ju

Yelehanka Ramachandramurthy

Chew Kok Wai

Yih Shung Lin

Charlie Wee Tay

Guo Li Mike

Jeffrey Chee Wei-Lun

Leung Ying Keung

Lee Yong Meng

Ravi Sundarensan

James Lee Young Meng

Yelehanka Ramachandamurthy Pradeep

Alan Cuthbertson

Jane C M Hui

An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

Semiconductor local interconnect and contact

A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.

Non-volatile memory manufacturing method using STI trench implantation

An integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

Integrated circuit with protected implantation profiles and method for the formation thereof

A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (f), and reduced gate delay.

MOSFET device with low gate contact resistance

An integrated circuit structure includes a semiconductor substrate and a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor is in contact with the thyristor.

Thyristor-based SRAM

A first method of reducing semiconductor device substrate effects comprising the following steps. Oor Oare selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

Process to reduce substrate effects by forming channels under inductor devices and around analog blocks

A lateral heterojunction bipolar transistor (HBT) comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

Self-aligned lateral heterojunction bipolar transistor

An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

Horizontal tram

DPN (decoupled plasma nitridation) is used to improve robustness of ultra thin gate oxides. Conventionally, this is followed by an anneal in pure helium to remove structural defects in the oxide. However, annealing under these conditions has been found to cause a deterioration of the electrical performance of devices. This problem has been overcome by annealing, in a 1:4 oxygen-nitrogen mixture (1,050&#xb0; C. at about 10 torr) instead of in helium or nitrogen oxide. This results in a gate oxide that is resistant to boron contamination without suffering any loss in its electrical properties.

Ultra-thin gate oxide through post decoupled plasma nitridation anneal

An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

An improved and new process of fabricating high dielectric constant MIM capacitors. These high dielectric constant MIM capacitor met all of the stringent requirements needed for both for both RF and analog circuit applications. For the high dielectric constant MIM capacitor, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of layers either 4/4, 2/2, and 1/1 artificial layers. Hence thickness of the film can be easily controlled. Enhancement of dielectric constant is because of interface. Dielectric constants near 900 can be easily achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques is used for this type layer growth process.

High K artificial lattices for capacitor applications to use in Cu or Al BEOL

A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

Horizontal TRAM and method for the fabrication thereof

A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.

Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy

Growing community of inventors

Singapore, Singapore

Jia Zhen Zheng