Powerchip Semiconductor Manufacturing Corporation

Jia-You Lin

Shou-Zen Chang

Pei-Hsiu Tseng

Yi-Hsung Wei

Chi-Wei Lin

Chih-Peng Lee

I-Shuan Wei

Hung-Hsun Lin

A manufacturing method of a SRAM memory device includes forming two transistors on a substrate, forming an inner dielectric layer covering the two transistors, forming contacts in the inner dielectric layer for coupling to source nodes of the two transistors, forming a metal interconnect structure on the inner dielectric layer, wherein a portion of an n-th metal layer of the metal interconnect structure is utilized as a lower metal layer, wherein n≥1. An opening is formed in the metal interconnect structure to expose the lower metal layer, and then a capacitor is formed in the opening. The capacitor includes the lower metal layer, a first electrode layer, a dielectric layer, a second electrode layer, and an upper metal layer from bottom to top. The upper metal layer is a portion of an m-th metal layer of the metal interconnect structure, wherein m≥n+1.

Manufacturing method of SRAM device

An SRAM memory device includes a substrate, a first transistor, a second transistor, a metal interconnect structure, and a capacitor. The metal interconnect structure is formed on the first and second transistors. The capacitor is disposed in the metal interconnect structure and coupled between the first transistor and the second transistor. The capacitor includes a lower metal layer, a first electrode layer, a dielectric layer, a second electrode layer, and an upper metal layer from bottom to top. The lower metal layer is coupled to a source node of the first transistor and a source node of the second transistor. The lower metal layer and an n-th metal layer in the metal interconnect structure are formed of a same material, wherein n&#x2265;1; the upper metal layer and an m-th metal layer in the metal interconnect structure are formed of a same material, wherein m&#x2265;n+1.

SRAM device and manufacturing method thereof

A SRAM device includes a substrate, at least one two-transistor static random access memory (2T-SRAM), an inner dielectric layer, a plurality of contacts, an inter-layer dielectric (ILD) layer, a plurality of vias, and a conductive line. The 2T-SRAM is disposed on the substrate, the inner dielectric layer covers the 2T-SRAM, and the contacts are disposed in the inner dielectric layer and coupled to the 2T-SRAM. The ILD layer covers the inner dielectric layer and the contacts, and the vias are disposed in the ILD layer and respectively coupled to the 2T-SRAM trough the corresponding contacts. The conductive line is disposed on the ILD layer and connects with the plurality of vias, wherein the thickness of the conductive line is less than or equal to one-tenth of the thickness of the via such that it can significantly reduce the coupling effect compared with the traditional bit line.

A bit line structure for two-transistor static random access memory (2T SRAM), including multiple bit lines extending over multiple 2T SRAMs in a first direction, wherein each bit line consists of multiple first portions and second portions extending in the first direction and electrically connecting with each other in an alternating manner, and the first portions and the second portions are in a first dielectric layer and a second dielectric layer respectively, and the first portions of each bit line correspond to the second portions of adjacent bit lines.

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Hsinchu, Taiwan

Jia-You Lin