Vanguard International Semiconductor Corporation

Jia-Rong Yeh

Yeh-Ning Jou

Shao-Chang Huang

Hsien-Feng Liao

Chih-Cherng Liao

Chih-Hsuan Lin

Hwa-Chyi Chiou

Chieh-Yao Chuang

Wei-Shung Chen

Ching-Wen Chen

Pang-Chuan Chen

Yi-Han Wu

An electrostatic discharge protection device includes a first well region, a second well region, a first doped region, and a first heavily doped region. The first well region and the second well region are disposed in a semiconductor substrate. The first doped region is disposed in the first well region and the second well region. The first heavily doped region is disposed in the first doped region in the first well region. The first well region and the first doped region have a first conductivity type, and the second well region and the first heavily doped region have a second conductivity type that is the opposite of the first conductivity type.

Electrostatic discharge protection devices

An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes an electrostatic discharge detection circuit, a discharge circuit, and a switch. The electrostatic discharge detection circuit detects whether an electrostatic discharge event occurs at the bounding pad to generate a first detection circuit. The discharge circuit receives the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the discharge circuit provides a discharge path between the bounding pad and a ground terminal according to the first detection signal. The switch is coupled between the core circuit and the ground terminal and controlled by the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the switch is turned off according to the first detection signal.

Integrated circuit and electrostatic discharge protection circuit thereof

A semiconductor structure includes a first P-well, a first P-type diffusion region, a first N-type diffusion region, a second P-type diffusion region, and a first poly-silicon layer. The first P-type diffusion region is deposited in the first P-well and coupled to a first electrode. The first N-well is adjacent to the P-well. The first N-type diffusion region is deposited in the first N-well. The second P-type diffusion region is deposited between the first P-type diffusion region and the first N-type diffusion region, which is deposited in the first N-well. The second P-type diffusion region and the first N-type diffusion region are coupled to a second electrode. The first poly-silicon layer is deposited on the first P-type diffusion region.

ESD protection devices

Growing community of inventors

Taipei, Taiwan

Jia-Rong Yeh