Taiwan Semiconductor Manufacturing Comp. Ltd.

Jia-Ren Chen

Hsun-Ying Huang

Yung-Cheng Chang

Chi-Hsun Hsieh

Shou Shu Lu

Yung-Fu Yeh

Juan-Lin Chen

Horng-Daw Shen

Cheng-Tsung Chen

Yu-Ping Chen

Chi-Yuan Liang

Chen-Hua Douglas Yu

Jean Wang

Henry Lo

Kewei Zuo

Chin-Chia Kuo

Hann-Huei Tsai

Simon Wang

Chien-Ming Sung

Hung Che Hsiue

Hann Huei Tsai

Li-De Hsu

Wei Hsiung Hsu

A semiconductor manufacturing line includes an inert environment selected from the group consisting essentially of an inert airtight wafer holder, an inert wafer transport channel, an inert production tool, an inert clean room, and combinations thereof.

Preventing contamination in integrated circuit manufacturing lines

A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region, the substrate having a front side and a backside. A co-implant process is performed along the backside of the substrate opposing a photosensitive element positioned along the front side of the substrate. The co-implant process utilizes a first pre-amorphization implant process that creates a pre-amorphization region. A dopant is then implanted wherein the pre-amorphization region retards or reduces the diffusion or tailing of the dopants into the photosensitive region. An anti-reflective layer, a color filter, and a microlens may also be formed over the co-implant region.

Co-implant for backside illumination sensor

A method for fabricating a semiconductor product first provides an embedded semiconductor product comprising: (1) a logic region having formed therein a logic field effect transistor device; (2) a memory region having formed therein a memory field effect transistor device; and (3) a kerf region having formed therein a kerf field effect transistor device. The method also provides for measuring for the embedded semiconductor product a gate electrode linewidth for each of the logic field effect transistor device, the memory field effect transistor device and the kerf field effect transistor device. The measured gate electrode linewidths may be compared among themselves or to specified target values for purposes photoexposure process control.

Multiple gate electrode linewidth measurement and photoexposure compensation method

A method and apparatus for performing a semiconductor process wafer drying process, the method provides a semiconductor wafer having a process surface disposed in an enclosed drying space following exposure of the process surface to water; supplying a solvent vapor to the drying space at a predetermined concentration from a solvent vapor source and at least one solvent vapor supply line; determining at least one of a solvent vapor concentration and a solvent vapor temperature in the drying space; and heating in response to the determined solvent concentration at least one of at least a portion of one of the solvent vapor source, the at least one solvent vapor supply line, and at the drying space to alter the solvent vapor concentration in the drying space.

Method to improve post wafer etch cleaning process

Growing community of inventors

Tainan, Taiwan

Jia-Ren Chen