International Business Machines Corporation

Globalfoundries Inc.

Jia Niu

Hongwei Dai

Yang Liu

Peng Ou

Wei Zhang

Jun Tan

Hong Wei Dai

Gongqiong Li

Gong Qiong Li

Zhenrong Shi

Jifeng Li

Yu Yun Song

A computer program product for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.

Static timing analysis in circuit design

The present invention discloses a method for simulating a digital circuit comprising: acquiring a gate-level netlist of the digital circuit, the gate-level netlist indicating at least one gate circuit included in the digital circuit and a connection relationship thereof; modifying the netlist, so as to add a timing and power model of each gate circuit, which is used to calculate a time delay generated when a signal inputted to the gate circuit passes through the gate circuit and a power consumed by the gate circuit during its operation; and simulating the digital circuit based on the modified netlist. By adding into the netlist the timing and power model of each gate circuit included in the digital circuit, a power estimation of the digital circuit can be performed while a function verification is performed on the digital circuit, thus function verification is seamlessly combined with the power estimation.

Method and apparatus for simulating a digital circuit

The present invention discloses a method for fixing hold time violations in circuits. The method comprises: creating a topology diagram of the circuit with a branch indicating a signal path where the hold time violation occurs in the circuit, and a node on the branch indicating a port of an element where the hold time violation occurs; dividing the circuit into a plurality of regions; and placing a hold time correction element selectively in a region corresponding to the node in the topology diagram to fix the hold time violation thereof, according to a circuit element density of the region corresponding to the node in the topology diagram. With this method there will be no new element in a region whose circuit element density is excessively large, and it is unnecessary to move an element which has been placed in the circuit and an input/output pin thereof.

Method and apparatus for physical-aware hold violation fixing

A method of for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.

The present invention relates to a method and an apparatus for estimating a clock skew. The method comprises: obtaining a basic clock skew of each clock tree in the circuit; judging whether two units are in a same clock domain; if they are in different clock domains, estimating the clock skew between units to be a larger one of basic clock skews of the clock trees corresponding to these two unit; if these two units are in the same clock domain, further judging whether they are in a same hierarchical logic block; if they are in different hierarchical logic blocks, estimating the clock skew between units to be the basic clock skew of the clock tree of these two units plus additional clock skew caused by different hierarchical logic blocks. The apparatus is corresponding to the method. With the method and apparatus, the clock skew in the circuit can be estimated more accurately, which improves the efficiency of circuit design.

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Shanghai, China

Jia Niu