Realtek Semiconductor Inc.

Jia-Ning Lou

Jun Yang

Jian Liu

Zhi-Xian Gao

A charge pump device includes first to third current source circuits, a first switch, and a second switch. The first current source circuit is implemented with a first type transistor, and provides a first current to an output node. The first switch is selectively turned on according to a first control signal. When the first switch is turned on, the second current source circuit drains a second current from the output node. The second switch is selectively turned on according to a second control signal. Each of the first switch and the second switch is implemented with a second type transistor, and a withstand voltage of the first type transistor is higher than a withstand voltage of the second type transistor. When the second switch is turned on, the third current source circuit drains a third current from the output node.

Charge pump device

A clock device includes a first phase interpolator circuit, a detector circuit, and a digital controller circuitry. The first phase interpolator circuit generates a second reference clock signal according to a first control signal and at least one first reference clock signal. The detector circuit generates an error signal according to a difference between a receiver signal and the second reference clock signal, in which the receiver signal is a receiver clock signal from a receiver circuit or an input signal that has been equalized by the receiver circuit. The digital controller circuitry generates the first control signal and a second control signal according to the error signal, and updates the second control signal according to a change of the first control signal, in which the second control signal is for generating a transmitter clock signal of a transmitter circuit.

Clock control device and clock control method

A clock and data recovery device includes a phase detector circuitry, an analog modulation circuitry, a serial-to-parallel converter circuit, a digital modulation circuitry, and an oscillator circuit. The phase detector circuitry detects a data signal according to first and second clock signals to generate an up signal and a down signal. The analog modulation circuitry generates a first adjustment signal according to the up signal and the down signal. The serial-to-parallel converter circuit generates a first control signal according to the up signal, and to generate a second control signal according to the down signal. The digital modulation circuitry generates a digital code according to the first and the second control signals, and to generate a second adjustment signal according to the digital code. The oscillator circuit generates the first and the second clock signals according to the first adjustment signal and the second adjustment signal.

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Suzhou, China

Jia-Ning Lou