Sandisk Technologies Inc.

Hmv Corporation

Jia Li

Bo Lei

Peng Wang

Yihang Liu

Dana Lee

Jiahui Yuan

Henry Chin

Jun Wan

Gary Allan Strobel

Long C Pham

Yanjie Wang

Abu Naser Zainuddin

Parth Amin

Sateesh Desireddi

Jianzhi Wu

Zhenni Wan

Keyur Payak

Behrang Bagheri

Ashwin D T

Harshul Gupta

The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The word lines are grouped in a plurality of layers. The memory device also includes circuitry that is configured to program the memory cells of a selected word line of the plurality of word lines. The circuitry is configured during programming to determine which layer of the plurality of layers the selected word line is located in. The circuitry is also configured to apply a programming voltage to the selected word line and apply pass voltages to a plurality of unselected word lines. For at least some of the unselected word lines, the pass voltage is a baseline pass voltage level that is adjusted by a layer-unique bias pass voltage.

VPASS auto layer compensation in a memory device

During a read operation for memory cells connected a selected word line, a memory system adjusts the overdrive voltage applied to word lines adjacent the selected word line in order to compensate for margin degradation between the erased data state and the lowest programmed data state.

Non-volatile memory with overdrive voltage zoning to compensate for reduced margins

An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.

Method to optimize first read versus second read margin by switching boost timing

A memory apparatus and method of operation are provided. The apparatus includes a page of memory cells connected to a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and strings and identifies the memory cells having the threshold voltage less than a primary demarcation threshold voltage of a series for demarcating between memory states in a page read. The control circuit also identifies the memory cells having the threshold voltage less than a secondary demarcation threshold voltage of the series. The control circuit supplies a near zero voltage to the strings of the memory cells identified as having the threshold voltages less than at least one of the primary and secondary demarcation threshold voltages to inhibit conduction currents while identifying the memory cells having the threshold voltage less than a tertiary demarcation threshold voltage.

Power saving and fast read sequence for non-volatile memory

Apparatuses and techniques are described for modifying program and erase parameters in a memory device in which memory cells can be operated in a single bit per cell (SLC) mode or a multiple bits per cell mode. In one approach, the stress on a set of memory cells in an SLC mode is reduced during programming and erasing when the number of program-erase cycles for the block in the SLC mode is below a threshold. For example, during programming, the program-verify voltage and program voltages can be reduced to provide a shallower than normal programming. During erasing, the erase-verify voltage can be increased while the erase voltages can be reduced to provide a shallower than normal erase. When the number of program-erase cycles for the block in the SLC mode is above the threshold, the program and erase parameters revert to a default levels.

Modifying program and erase parameters for single-bit memory cells to improve single-bit/multi-bit hybrid ratio

Apparatuses, systems, methods, and computer program products are disclosed for dynamic read table generation. One apparatus includes a set of non-volatile storage cells. A controller for a set of non-volatile storage cells is configured to, in response to unsuccessfully reading a storage cell of the set of non-volatile storage cells using a parameter, read the storage cell using one or more shifted values. A controller for a set of non-volatile storage cells is configured to, in response to successfully reading a storage cell using one or more shifted values, add the one or more shifted values to a storage device.

Dynamic read table generation

Oocydin A is a mono-chlorinated lipophilic macrocyclic lactone that was isolated from a strain of that produces oocydin A in culture. Oocydin A has a molecular mass of 470, contains one atom of chlorine, a carboxyl group, and a tetrahydrofuran ring internal to a larger macrocyclic ring. Minimum inhibitory concentrations of circa 0.03 &mgr;g ml were noted for oocydin A against phytopathogenic Oomycetes. Oocydin A can be used as an anti-Oomycete in agricultural applications for crop protection.

Oocydin and methods of use for protection of plants from Oomyocyte pathogens

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San Francisco, CA, United States of America

Jia Li