International Business Machines Corporation

Applied Materials, Inc.

Sony Corporation

Sony Electronics Inc

Jia Lee

Li-Qun Xia

Stephen McConnell Gates

John Anthony Fitzsimmons

Darryl D Restaino

Ping Xu

Sarah L Lane

Srinivas D Nemani

Ellie Y Yieh

Hichem M'Saad

Mihaela A Balseanu

Mei-Yee Shek

Matthew S Angyal

Habib Hichri

Dian Sugiarto

Edward Paul Barth

Francimar Campana-Schmitt

Theodorus E Standaert

Son Van Nguyen

Takeshi Nogami

Terry Allen Spooner

Vincent James McGahay

Stephen Edward Greco

Michael Santiago Cox

Vladimir Zubkov

Tzu-Fang Huang

Rongping Wang

Glenn A Biery

Thomas H Ivers

Ann H McDonald

Kensaku Ida

Isabelita Roflox

Amir Hamed Al-Bayati

William Francis Landers

Charles Robert Davis

Sanjit Kumar Das

Ishing Lou

High tensile stress in a deposited layer, such as a silicon nitride layer, may be achieved utilizing one or more techniques employed either alone or in combination. In one embodiment, a silicon nitride film having high tensile stress may be formed by depositing the silicon nitride film in the presence of a porogen. The deposited silicon nitride film may be exposed to at least one treatment selected from a plasma or ultraviolet radiation to liberate the porogen. The silicon nitride film may be densified such that a pore resulting from liberation of the porogen is reduced in size, and Si&#x2014;N bonds in the silicon nitride film are strained to impart a tensile stress in the silicon nitride film. In another embodiment, tensile stress in a silicon nitride film may be enhanced by depositing a silicon nitride film in the presence of a nitrogen-containing plasma at a temperature of less than about 400&#xb0; C., and exposing the deposited silicon nitride film to ultraviolet radiation.

Method to increase tensile stress of silicon nitride films using a post PECVD deposition UV cure

High tensile stress in a deposited layer such as silicon nitride, may be achieved utilizing one or more techniques, employed alone or in combination. High tensile stress may be achieved by forming a silicon-containing layer on a surface by exposing the surface to a silicon-containing precursor gas in the absence of a plasma, forming silicon nitride by exposing said silicon-containing layer to a nitrogen-containing plasma, and then repeating these steps to increase a thickness of the silicon nitride created thereby. High tensile stress may also be achieved by exposing a surface to a silicon-containing precursor gas in a first nitrogen-containing plasma, treating the material with a second nitrogen-containing plasma, and then repeating these steps to increase a thickness of the silicon nitride formed thereby. In another embodiment, tensile film stress is enhanced by deposition with porogens that are liberated upon subsequent exposure to UV radiation or plasma treatment.

A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.

Integration process for fabricating stressed transistor structure

A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter 'SiCOH') in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, &#x2014;CH&#x2014; crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH+CHstretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCHbonding of greater than about 2.0, and a peak area for Si&#x2014;O&#x2014;Si bonding of greater than about 60%, and a porosity of greater than about 20%.

Advanced low dielectric constant organosilicon plasma chemical vapor deposition films

An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

Reliable low-k interconnect structure with hybrid dielectric

A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer has a compressibility that varies as a function of the amount of dopant present in the gas mixture during later formation.

Method of depositing dielectric films

An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%&#x2013;10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.

Low-k interlevel dielectric layer (ILD)

An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof

A method of forming a silicon carbide layer, a silicon nitride layer, an organosilicate layer is disclosed. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a fluorine source in the presence of an electric field. The silicon nitride layer is formed by reacting a gas mixture comprising a silicon source, a nitrogen source, and a fluorine source in the presence of an electric field. The organosilicate layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, an oxygen source and a fluorine source in the presence of an electric field. The silicon carbide layer, the silicon nitride layer and the organosilicate layer are all compatible with integrated circuit fabrication processes.

Fluorine-containing layers for damascene structures

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San Jose, CA, United States of America

Jia Lee