Faraday Technology Corporation

Jia-Jio Huang

Han-Chi Liu

Yuan-Hsun Chang

Chien-Hui Chuang

Kun-Cheng Wu

Cheng-Chung Chou

Chih-Yang Peng

Alvin Hsin-Hung Chen

Yi-Ping Lin

Hanping Chen

Jim Jyh-Herng Wang

A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.

Methodology and system for setup/hold time characterization of analog IP

A poly fuse trimming circuit. The poly fuse trimming circuit comprises a poly fuse and a silicon controlled rectifier (SCR) device. The poly fuse is coupled between a first fixed potential and an output node. The SCR device is controlled by a trimming signal and has an anode coupled to the output node and a cathode coupled to a second fixed potential.

Poly fuse trimming circuit

A voltage regulator apparatus, wherein two transistors are coupled to an output terminal of a voltage regulator, so as to improve the transient response of output voltage and increase the stability of the output voltage. Besides, it avoids the use of an external capacitor.

Voltage regulator apparatus

A switched capacitor circuit of a pipeline analog to digital converter. The pipeline ADC includes a clock generator, a signal reference circuit, and a plurality of switched capacitor circuit. Each switched capacitor includes an operational amplifier, a first sampling capacitor, a first signal input switch, a first reference input switch, a first reference reset switch, and a first feedback network. A method for operating the switched capacitor circuit includes after the first reference input switch turning off, turning on the first signal input switch to transmit a first input signal to the first sampling capacitor and turning on the first reference reset switch to transmit a common signal to a second terminal of the first reference input switch, turning off the first reference rest switch then turning off the first signal input switch, and after the first signal input switch turning off, turning on the first reference input switch.

Switched capacitor circuit of a pipeline analog to digital converter and a method for operating the switched capacitor circuit

A successive approximation analog-to-digital converter is used for converting an analog input signal into a corresponding digital output signal. The successive approximation analog-to-digital converter has a successive approximation register for storing a first digital bit stream and a second digital bit stream that are related to the analog input signal, and a digital-to-analog converter for generating a first reference voltage and a second reference voltage according to the first and second digital bit streams. The digital-to-analog converter has a first voltage divider and a second voltage divider. The first voltage divider drives the first reference voltage approaching the analog input signal to establish the first digital bit stream, and the second voltage divider drives the second reference voltage approaching the analog input signal to establish the second digital bit stream. Finally, the first and second digital bit streams are averaged to generate the digital output signal.

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Hsinchu, Taiwan

Jia-Jio Huang