Taiwan Semiconductor Manufacturing Comp. Ltd.

Jia-Guei Jou

Chi-Ming Tsai

Dong-Hsu Cheng

Chi-Ta Lu

Peng-Ren Chen

Chin-Min Huang

Yin-Chuan Chen

Ching-Hung Lai

Chih-Chung Huang

Ru-Gun Liu

Tsai-Sheng Gau

Wen-Chun Huang

Chih-Chiang Tu

Ming-Hui Chih

Chia-Ping Chiang

Kuan-Chi Chen

Yi-Hsien Chen

Huang-Ming Wu

Yi-Chiuan Luo

Yung-Pei Chin

Jiun-Hao Lin

A method for forming a photomask includes following operations. A first photomask is received. The first photomask includes a first pattern and a first scattering bar. The first photomask is used to remove a first portion of a target layer to form a first opening and a second opening. The first opening corresponds to the first pattern, and the second opening corresponds to the first scattering bar. A second photomask is received. The second photomask includes a second pattern. The second photomask is used to remove a second portion of the target layer to form a third opening. The third opening corresponds to the second pattern. The second opening is widened to form the third opening using the second photomask.

Photomask and method for manufacturing photomask and semiconductor structure thereof

A method for forming a photomask is provided. The method includes: receiving an initial layout, the initial layout comprising a first pattern and a second pattern; decomposing the initial layout into a first layout including the first pattern and a second layout including the second pattern; inserting a third pattern into the first layout; overlapping the first layout including the first pattern and the third pattern to the second layout including the second pattern; increasing a width of the third pattern in the first layout overlapping the second pattern in the second layout to form a fourth pattern in the first layout; and outputting the first layout comprising the first pattern, the third pattern and the fourth pattern into a first photomask.

Present disclosure provide a method for fabricating a mask, including obtaining a target pattern to be imaged onto a substrate, providing a first scattering bar and a second scattering bar adjacent to consecutive edges of the target pattern, identifying a first length of the first scattering bar and a second length of the second scattering bar, connecting the first scattering bar and the second scattering bar when any of the first length and the second length is smaller than a predetermined value, identifying a separation between the first scattering bar and the second scattering bar subsequent to identifying the first length and the second length, disposing the first scattering bar and the second scattering bar in a first fashion when the separation is equal to zero, and disposing the first scattering bar and the second scattering bar in a second fashion when the separation is greater than zero.

Mask and method for fabricating the same

A method for forming a photomask is provided. The method includes: receiving an initial layout including a plurality of first patterns and a plurality of second patterns; decomposing the initial layout into a first layout including the plurality of first patterns and a second layout including the plurality of second patterns; inserting a plurality of third patterns into the first layout, wherein each of the plurality of third patterns is adjacent to at least one of the plurality of first patterns; comparing the first layout and the second layout; identifying a fourth pattern as an overlapping portion of the plurality of third patterns overlapping one of the plurality of second patterns; increasing a width of the fourth pattern; and outputting the first layout including the first patterns, the third patterns and the fourth patterns into a first photomask.

Method for manufacturing photomask and semiconductor thereof

A method of preparing mask data, the method begins with performing a logic operation to a design layout, and an optical proximity correction (OPC) is performed to the design layout to form an OPC feature. The OPC feature has a first jog and a second jog on a line, and the first jog is larger than the second jog in width. The OPC feature is resized to form a resized first jog and a resized second jog on the line if a width ratio of the first jog to the second jog being smaller than a predetermined value.

Apparatus and method for e-beam writing

The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced.

Structure and method for E-beam writing

A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result.

Layout decomposition method

A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies.

Mask making with error recognition

The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.

Growing community of inventors

Taipei, Taiwan

Jia-Guei Jou