Changxin Memory Technologies, Inc.

The 38Th Research Institute of China Electronics Technology Group Corporation

38Th Research Institute, China Electronics Technology Group Corporation

Jia Fang

Zhongming Liu

Yexiao Yu

Longyang Chen

Xinman Cao

Tao Jiang

Qian Chen

Jiayun Zhang

Xiaolin Zhang

Yinglu Wan

Zichao Li

Yuefei Dai

Quan Wang

Mouping Jin

Qingchao Zhu

Weiying Cai

The present application discloses a semiconductor structure and a method for fabrication. This technique improves the stability of the bit line structure. The semiconductor structure is formed in a bit line trench in a substrate, it includes: a bit line conductive layer formed in the bit line trench, and the top surface of the bit line conductive layer is higher the top surface of the substrate; a barrier layer formed at least partially between the bit line conductive layer and the inner wall of the bit line trench; and an isolation layer formed on top of the bit line conductive layer.

Method of forming a bit line structure

A method for manufacturing a semiconductor structure includes: providing a substrate, a first mask and a second mask, etching the substrate by respectively using the first mask and the second mask, so as to form first grooves and second grooves on the substrate, wherein regions, in the substrate, where the first grooves and the second grooves are located form bit line grooves; and forming a conductive layer in each of the bit line grooves.

Method for manufacturing semiconductor structure, and semiconductor structure

A semiconductor structure and a manufacturing method thereof are provided. The method includes following operations. A substrate including active regions and isolation regions is provided. First trench structures are formed on the substrate, the first trench structure passing through the active region and the isolation region. Bit line contact structures are formed in the first trench structures. Bit line structures are formed on the bit line contact structures, at least part of the bit line structure being positioned in the first trench structure. Bit line protection structures are formed on the bit line structures, the bit line protection structure at least covering an upper surface of the bit line structure. Capacitor contact assemblies are formed, the capacitor contact assembly including a first capacitor contact structure and a second capacitor contact structure which covers an upper surface and part of a side wall of the first capacitor contact structure.

Semiconductor structure and manufacturing method thereof

A method for manufacturing the mask structure includes: forming a first mask layer, a first buffer layer, a second mask layer, and a second buffer layer sequentially stacked from bottom to top; patterning the second buffer layer and the second mask layer, as to obtain a first pattern structure, the first pattern structure exposes a part of the first buffer layer; forming a first mask pattern on sidewalls of the first pattern structure; forming a carbon plasma layer as a protective layer on an exposed part of an upper surface of the first buffer layer; removing the first pattern structure; and removing a remaining protective layer.

Method for manufacturing mask structure, semiconductor structure and manufacturing method thereof

A method for manufacturing a semiconductor structure includes: a substrate with a groove structure formed therein is provided; a laminated structure is formed on the substrate, which includes a first conductive material layer, a second conductive material layer and an insulating material layer from bottom up, and the first conductive material layer fills the groove structure and covers the surface of the substrate; the insulating material layer, the second conductive material layer and the first conductive material layer are sequentially etched to form a bit line structure, in which a process of etching the first conductive material layer includes a first etching stage and a second etching stage, such that a bottom width of the first pattern structure located in the groove structure is not smaller than that of the first pattern structure located outside the groove structure.

A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure comprises: providing a substrate, comprising a polysilicon layer, a first conductive layer, a first dielectric layer, a mask layer, and a sacrificial layer sequentially formed thereon, wherein the sacrificial layer has a plurality of first trenches distributed at intervals; forming a first insulating layer on the sacrificial layer; forming a protective layer, the protective layer only covering a surface of the first insulating layer above the top surface of the sacrificial layer; removing the protective layer, part of the first insulating layer, the sacrificial layer, and part of the mask layer to form a first pattern layer; and removing part of the first dielectric layer, part of the first conductive layer, and part of the polysilicon layer by using the first pattern layer as a mask to form a BL structure.

The semiconductor structure manufacturing method includes the steps of: providing a substrate with bit line contact regions and isolation regions located between adjacent bit line contact regions; forming a groove in the substrate, the bottom of the groove exposes the bit line contact region and the isolation region adjacent to the bit line contact region; forming a contact region isolation layer covering at least sidewalls of the groove; and forming a contact region to cover the contact region isolating the surface of the layer and filling the bit line contact layer of the groove, the bit line contact layer being in contact with the bit line contact region at the bottom of the groove; forming a bit line layer on the bit line contact layer. The invention avoids damage to the sidewalls of the active region in the substrate.

Method for forming a semiconductor memory structure

The present application relates to a semiconductor structure and a method of manufacturing the same. The method includes: providing a substrate; forming a bitline contact hole located in the substrate, and a non-metal conductive layer with which a surface of the substrate is covered and the bitline contact hole is filled, the non-metal conductive layer provided with a first opening therein, the first opening aligned with the bitline contact hole; forming a metal conductive layer, with which a surface of the non-metal conductive layer is covered; forming an insulation layer, with which a surface of the metal conductive layer surface is covered; and etching the insulation layer, the metal conductive layer, and the non-metal conductive layer to form a bitline structure.

Semiconductor structure and method of manufacturing same

The present disclosure provides a broadband dual-polarized solar cell antenna and an antenna array. The broadband dual-polarized solar cell antenna includes an antenna dipole layer, an isolation layer, a solar cell layer, and a ground that are arranged sequentially from top to bottom, where the antenna dipole layer is connected to the ground and a radio frequency (RF) coaxial connector through a metal feeding probe structure, the solar cell layer is placed on the ground, the isolation layer is located between the antenna dipole layer and the solar cell layer, and the isolation layer is made of a transparent material. The present disclosure is small in sunlight shielding and high in transparency, and has a broadband dual-polarized wide-angle scanning capability, which ensures performance of the antenna and power generation efficiency of the solar cell, and is highly applicable in engineering.

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Hefei, China

Jia Fang