University of Arkansas

Other

Nanowatt Design, LLC

Jia Di

Scott Christopher Smith

Zhong Yu Chen

Ron Foster

Matthew Leftwich

Jerry Frenkil

Chandler Bernard

Andrew Lloyd Suchanek

Aaron Arthurs

Multiple polymorphic Multi-Threshold NULL Convention Logic gates that exhibit one function under a higher supply voltage, and the other function under a lower supply voltage and asynchronous polymorphic circuits able to implement two distinctive functionalities controlled by the supply voltage.

Asynchronous polymorphic logic gate design

A circuit stacking multiple asynchronous circuit components, specifically Multi-Threshold NULL Convention Logic (MTNCL) circuit components, with an overall power supply equal to the multiples of the original VDD.

Asynchronous circuit stacking for simplified power management

A multi-rail module having mutually exclusive outputs. The module includes first and second-rail logic circuits, first and second-rail driver circuits, and a PMOS transistor sourcing Vto both the first and second driver circuits. The first-rail logic circuit is coupled to Vand ground and has a first logic input and a first logic output. The second-rail logic circuit is coupled to Vand ground and has a second logic input and a second logic output. The first-rail driver circuit is coupled to ground, receives the first logic output, and has a first-rail output Q. The second-rail driver circuit is coupled to ground, receives the second logic output, and has a second-rail output Q. The PMOS transistor has a gate driven by a SLEEP signal.

Single component sleep-convention logic (SCL) modules

A Static Sleep Convention Logic (SSCL) circuit. The circuit improves upon Multi-Threshold NULL Convention Logic (MTNCL), disclosed in U.S. Pat. No. 7,977,972, by utilizing the SECRII architecture along with the Bit-Wise MTNCL technique, to produce a new SSCL gate without an nsleep input, which yields a smaller and faster circuit that utilizes less energy per operation than the patented SMTNCL gate design, while only very slightly increasing leakage power during sleep mode.

Multi-threshold sleep convention logic without nsleep

A multi-threshold null convention logic circuit. The circuit includes a first circuit, a first high-threshold transistor coupled to V, and an inverter receiving power from the first high-threshold transistor, driven by the first circuit, and including an output.

Ultra-low power multi-threshold asynchronous circuit design

A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.

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Fayetteville, AR, United States of America

Jia Di