Taiwan Semiconductor Manufacturing Comp. Ltd.

Parabellum Strategic Opportunities Fund LLC

Jia-Chuan You

Chih-Hao Wang

Chia-Hao Chang

Yu-Ming Lin

Tien-Lu Lin

Kuo-Cheng Chiang

Wai-Yi Lien

Lin-Yu Huang

Shi Ning Ju

Sheng-Tsung Wang

Li-Yang Chuang

Wei-Hao Wu

Shih-Chuan Chiu

Huan-Chieh Su

Kuan-Ting Pan

Li-Zhen Yu

Chun-Yuan Chen

Kuan-Lun Cheng

Zhi-Chang Lin

Yi-Hsun Chiu

Shi-Ning Ju

Yi-Hsiung Lin

Yu-Xuan Huang

Yi-Ruei Jhan

Gwan-Sin Chang

Ke-Jing Yu

Ching Hsueh

Chia-Hao Kuo

Jhon Jhy Liaw

Ching-Wei Tsai

Jung-Chien Cheng

Chu-Yuan Hsu

Kuo-Cheng Ching

Cheng-Chi Chuang

Chun-Hsiung Lin

Guan-Lin Chen

Kuo-cheng Chiang

Che-Chen Wu

Yuan-Hsiang Wu

Chia-Hao Wang

A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.

Gate isolation structure

Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

Low parasitic capacitance contact structure

A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Source/drain metal contact and formation thereof

A method includes a gate electrode, a first spacer, a second spacer, a metal cap, and a dielectric structure. The gate electrode is over a substrate. The first spacer structure extends along a first sidewall of the gate electrode. The second spacer structure extends along a second sidewall of the gate electrode. The metal cap is over the gate electrode. The dielectric structure is over the gate electrode, the first spacer structure, and the second spacer structure. The dielectric structure has a top segment higher than a top segment of the metal cap.

Semiconductor device with metal cap on gate

A semiconductor device includes an active area extending in a first direction over a substrate, the active area including at least one conductive path extending from a source region, through a channel region, to a drain region; and a gate dielectric on a surface of the at least one conductive path in the channel region. The semiconductor device also includes an isolating fin at a first side of the active area, the isolating fin having a first fin region having a first fin width adjacent to the source region, a second fin region having a second fin width adjacent to the channel region, and a third fin region having the first fin width adjacent to the drain region; and a gate electrode against the gate dielectric in the channel region.

Semiconductor device with trimmed channel region and method of making the same

A semiconductor device includes a semiconductor substrate, a gate electrode, a source/drain contact, a conductive structure, and a dielectric liner. The semiconductor substrate has a channel region and a source/drain region. The gate electrode is over the channel region. The source/drain contact is over the source/drain region. The conductive structure is over a top surface of the source/drain contact. The dielectric liner surrounds the conductive structure and is over the top surface of the source/drain contact.

Semiconductor device

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.

Isolation structures of semiconductor devices

Semiconductor device structures and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack formed over the substrate. The semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. In addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.

Semiconductor device structure

A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

Semiconductor device structure and method for forming the same

Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.

Self-aligned metal gate for multigate device and method of forming thereof

A semiconductor device structure includes a first channel structure and a second channel structure over a substrate. The semiconductor device structure also includes a first gate stack over the first channel structure and a second gate stack over the second channel structure. The first gate stack and the second gate stack have a first work function layer and a second work function layer, respectively. The first work function layer and the second work function layer are made of a same material. The second gate stack has a first protruding portion and a second protruding portion, and each of the first protruding portion and the second protruding portion extends upwards and extend away from the second channel structure. The first protruding portion and the second protruding portion are spaced apart from each other, and half of the first gate stack is wider than the first protruding portion.

Semiconductor device structure with metal gate stack

A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

Gate isolation feature and manufacturing method thereof

A semiconductor device with reduced contact resistance is provided. The semiconductor device includes a substrate having a channel region and a source/drain region, a source/drain contact structure over the source/drain region, a conductive structure over the source/drain contact structure, an interlayer dielectric (ILD) layer surrounding the conductive structure and source/drain contact structure, a dielectric liner between the ILD layer and the conductive structure, and a diffusion barrier between the dielectric liner and the conductive structure.

Glue layer etching for improving device performance and providing contact isolation

A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Contact resistance between via and conductive line

A device includes a gate structure, first and second gate spacers, source/drain regions, a refill metal structure, and a first dielectric liner. The gate structure is on a substrate. The first and second gate spacers are on opposite sides of the gate structure, respectively. The source/drain regions are spaced part from the gate structure at least in part by the first and second gate spacers. The refill metal structure is on the gate structure and between the first and second gate spacers. The first di electric liner is atop the gate structure. The first dielectric liner interposes the refill metal structure and the first gate spacer.

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Taoyuan County, Taiwan

Jia-Chuan You