Intel Corporation

Marvell International Limited

Jia Bao

Bin Yang

Mohammad R Haghighat

Zi Gu

Changliang Wang

Premanand Sakarda

Tao Xu

Yifan Zhang

Yong Yao

Moinul H Khan

Yao Zu Dong

Zhen Zhou

Mingqiu Sun

Lei Li

Hu Tiger Chen

Michael D Rosenzweig

Shoumeng Yan

Minda Zhang

Ke Ding

Tianyou Li

Raul Zegers Diaz

Priya N Vaidya

Wei Hu

Dong-Yuan Chen

Marlon Moncrieffe

Shuo Liu

Zhifang Long

Scott B Peirce

Chao Xie

Fengqian Gao

Xiaocheng Marc Mao

Xiaokang Qin

Yifei Xue

Qiming Shi

Beiyuan Hu

Yipeng Yao

Tianmi Chen

Yanmin Zhang

Raul Diaz

Mingwei Shi

Palanisamy Mohanraj

Jim Zhou

Chun Zhu

Systems, apparatuses and methods may provide for source device technology that identifies a plurality of object regions in a video frame, automatically generates context information for the video frame on a per-object region basis and embeds the context information in a signal containing the video frame. Additionally, playback device technology may decode a signal containing a video frame and embedded context information, identifies a plurality of object regions in the video frame based on the embedded context information, and automatically selects one or more post-processing configurations for the video frame on a per-object region basis.

Technology to use video source context information in post-processing operations

An electric vehicle computing sharing system () is adapted to receive a signal indicating the electric vehicle () is connected to a charging station (). The computing sharing system () may be further adapted to receive information about the electric vehicle (). The computing sharing system () may be further adapted to determine a predicted charging duration () for the electric vehicle (). The computing sharing system () may be further adapted to identify a task for execution by a computing resource of the electric vehicle () based on the predicted charging duration (). The computing sharing system () may be further adapted to transmit the task to the electric vehicle (). The computing sharing system () may be further adapted to receive a result for the task from the electric vehicle ().

Secure and efficient computing sharing for electric automobiles

Methods, apparatus, systems and articles of manufacture to deduplicate duplicate memory in a cloud-computing environment are disclosed herein. An example apparatus to deduplicate duplicate memory comprises a parser to parse process information corresponding to instances of an application, a group generator to group process information into application groups based on the process information indicating instances corresponding to the same directory paths and application names, a data structure generator to generate a pair of binary search trees for an application group, and a merge controller to deduplicate duplicate memory contents detected in the application group.

Methods and apparatus to deduplicate duplicate memory in a cloud computing environment

Systems, apparatuses and methods may provide for technology that sends a first message via an input output (IO) link, wherein the first message includes a first rendering asset and an identifier (ID) associated with the first rendering asset. The technology may also exclude a second rendering asset from a second message in response to the ID being shared by the first rendering asset and the second rendering asset and send the second message via the IO link, wherein the second message includes the ID. In one example, the ID is a hash ID.

Asset caching in cloud rendering computing architectures

Apparatuses, methods and storage medium associated with multi-phase/level boot technology, are disclosed herein. In embodiments, a method may include resuming an initial execution image of a computing platform from persistent storage to execute an initial task; and subsequently, resuming a full execution image of the computing platform from the persistent storage to execute one of a plurality of operational tasks. Other embodiments are also described and claimed.

Computing method and apparatus with multi-phase/level boot

An application and system fast launch may provide a virtual memory address area (VMA) container to manage the restore of a context of a process, i.e., process context, saved in response to a checkpoint to enhance performance and to provide a resource efficient fast launch. More particularly, the fast launch may provide a way to manage, limit and/or delay the restore of a process context saved in response to a checkpoint, by generating a VMA container comprising VMA container pages, to restore physical memory pages following the checkpoint based on the most frequently used or predicted to be used. The application and system fast launch with the VMA container may avoid unnecessary input/output (I/O) bandwidth consumption, page faults and/or memory copy operations that may otherwise result from restoring the entire context of a VMA container without regard to frequency of use.

Application and system fast launch by virtual address area container

Dynamic processor core switching is described. In embodiments, a multi-core processor system can include a first processor core that executes computer instructions at a first processing rate, and can include at least a second processor core that executes the computer instructions at a second processing rate, where the second processing rate is different than the first processing rate. A core profiler can generate system profile data that is evaluated to determine when a core-switch manager initiates switching execution of the computer instructions from the first processor core to the second processor core while the computer instructions are being executed.

Dynamic processor core switching

An embodiment of the present invention includes a multi-core processor that processes video data. The control core controls a first processing core to process a first set of data blocks of an image frame according to a stairstep pattern. The control core detects, while the first processing core is processing the first set, that a triggering data block has been processed in the first set. The control core controls, while the first processing core is processing the first set, a second processing core to process a second set of data blocks using information from the triggering data block. By processing data blocks in the stairstep pattern, cache hit rate is improved, resulting in improved video decoder performance.

System and method of video coding using adaptive macroblock processing

Apparatus having corresponding methods comprise a processing core performance monitoring module adapted to receive indications of performance levels of a plurality of processing cores, the plurality of processing cores comprising a central processing unit (CPU), a video accelerator, and a graphics accelerator; a video accelerator performance monitoring module adapted to receive an indication of a performance level of the video accelerator; a graphics accelerator performance monitoring module adapted to receive an indication of a performance level of the graphics accelerator; and a processor core management module adapted to dynamically allocate at least one of a pre-processing task and a post-processing task of a multimedia workload to any one of the video accelerator, the graphics accelerator, and the CPUprocessing cores based on the performance levels of the video accelerator, the graphics accelerator, and the CPU.

Dynamic processing core selection for pre- and post-processing of multimedia workloads

In video decoding using the H.264/AVC standard, the computation of an inverse 4&#xd7;4 integer transform of a coefficient matrix derived by variable length decoding may be carried out using data reduction techniques to reduce the computation load. If the index value of the highest-indexed nonzero coefficient in the matrix is three or higher, the transform is computed conventionally, using two 1D transform operations separated by a transpose operation, and followed by rounding and shifting. If the index value of the highest-indexed nonzero coefficient in the matrix is zero (including the case where there is no nonzero coefficient), the inverse integer transform operation includes only rounding and shifting of that coefficient. If the index value of the highest-indexed nonzero coefficient in the matrix is one or two, then the inverse integer transform operation can be performed using a single integrated 2D transform followed by rounding and shifting.

Fast inverse integer transform for video decoding

A method of filtering a pixels along a block edge during decoding of compressed VC-1 video includes loading edge segments with pixels along the sides of a block edge into registers, calculating a selection mask for a third pixel pair, and filtering the pixels in the edge segments simultaneously in the registers, if the selection mask meets a predetermined criteria. In another embodiment, a method of filtering pixels along a block edge during decoding of compressed VC-1 video includes loading edge segments with pixels along the side of a block edge into registers, swapping a first pair of the pixels with a second pair of the pixels, where each of the pairs of pixels are third pixel pairs of their respective segments, filtering the pairs of pixels simultaneously in the registers, and filtering the remaining pixels of the respective edge segments, if the results of filtering the third pixels pairs meet a predetermined criteria. The registers may be single instruction multiple data (SIMD) registers used with a Wireless MMX processor.

Fast in-loop filtering in VC-1

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Shanghai, China

Jia Bao