Macronix International Co., Ltd.

Ji-Yu Hung

Shuo-Nan Hung

E-Yuan Chang

Chun-Hsiung Hung

Hsin-Yi Ho

Wen-Chiao Ho

Shih-Lin Huang

Kai-Hsiang Chiang

Fu-Tsang Wang

Systems, methods, circuits, and apparatus for managing data transfer in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first circuit, a data bus coupled to the first circuit, and a precharging circuit coupled to the data bus. The precharging circuit is configured to precharge the data bus to have a predetermined voltage before data is transferred through the data bus. The first circuit is conductively coupled to the data bus by applying a control voltage to the first circuit. The control voltage is determined based on the predetermined voltage.

Managing data transfer in semiconductor devices

Systems, methods, circuits, and apparatus for managing page buffer circuits in memory devices are provided. In one aspect, a memory device includes a memory cell array, a page buffer circuit including a plurality of page buffers, and a cache data latch (CDL) circuit including a plurality of caches coupled to the plurality of page buffers through a plurality of data bus sections. The plurality of data bus sections are configured to be conductively connected together as a data bus for data transfer. Each data bus section corresponds to a page buffer in the page buffer circuit and is configured to conductively separate from at least one adjacent data bus section for data sensing in the memory cell array.

Managing page buffer circuits in memory devices

A memory device includes a memory cell array including memory cells; a page buffer circuit including a plurality of page buffers coupled to the memory cell array, each page buffer including a plurality of latches and an internal data line (IDL) arranged to couple to the plurality of latches; and a cache circuit including a plurality of caches. The IDLs of the plurality of page buffers are configured to be conductively connected together to form a data bus (DBUS) that conductively connects the page buffer circuit to the cache circuit for data transfer.

Page buffer circuits in memory devices

A memory such as a 3D NAND array, having a page buffer having page buffer cells coupled to bit lines has a search word input such as a search word buffer coupled to word lines. A circuit, such as string select gates, is provided to connect a selected set of memory cells in the array to the page buffer. The page buffer includes sensing circuitry configured to apply a match sense signal to a latch in a plurality of storage elements for a stored data word and an input search word. Logic circuitry uses storage elements in the plurality of storage elements of the page buffer to accumulate the match sense signals output by the sensing circuitry over a sequence matching a plurality stored data words to one or more input search words. A match for a search is based on a threshold and the accumulated match sense signals.

Page buffer counting for in-memory search

The disclosed technology teaches a memory device with memory cells, each with a sense circuit with an input node in current flow communication, a BLC transistor, a transfer transistor, a current source transistor, and an output circuit to generate data based on a voltage on the sensing node. Also disclosed is a sensing sequence in which control circuits apply BLC voltage to the BLC transistor, transfer voltage to the transfer transistor and current control voltage to the current source transistor to provide a charging current to the BL, and to adjust the current control voltage to provide a keeping current on the BL from the current source transistor, and to apply a read voltage to a selected memory cell on the bit line. Additionally included is applying a timing signal to the output circuit to generate the data based on a voltage on the sensing node.

Low noise bit line circuits

A memory device such as a page mode NAND flash, including a page buffer with first and second-level buffer latches is operated using a first pipeline stage, to transfer a page to the first-level buffer latches; a second pipeline stage, to clear the second-level buffer latches to a third buffer level and transfer the page from the first-level buffer latches to the second-level buffer latches; and a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing a second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.

Page buffer structure and fast continuous read

A memory device includes a memory array and bit lines coupled to the memory array. A voltage source is included for supplying a voltage used during a charging operation. Bit line clamp transistors, such as bit line clamp transistors, are coupled to the voltage source, and configured to regulate current on the corresponding bit lines in response to a bit line control signal. A control circuit generates the bit line control signal in response to a feedback signal. A feedback circuit is provided that is coupled to the voltage source and produces the feedback signal. The feedback circuit senses load of the bit lines being charged. The load of the bit lines being charged can be sensed by sensing the magnitude of the current from the voltage source during the charging operation.

Memory with controlled bit line charging

A sensing amplifier includes a first bit line driver, a second bit line driver and a third bit line driver. The first bit line driver sets a first bit line for a fast-pass-write (FPW) operation. The second bit line driver sets a second bit line for a first operation rather than the FPW operation. The third bit line driver sets a third bit line for a second operation rather than the FPW operation. The first bit line is arranged between the second bit line and the third bit line, and the second bit line driver and the third bit line driver respectively adjust voltage statuses of the second bit line and the third bit line to rise a voltage level of the first bit line by a compensated level.

Sense amplifier and method for bit line voltage compensation thereof

A page buffer circuit is coupled to a bit line of a memory array. The page buffer circuit includes a latch storing different data during different phases of a multi-phase program operation. A preparation phase is after the program phase and after the program verify phase of the present multi-phase program operation. For the preparation phase, the control circuitry causes the latch to store the preparation data indicating whether to program the memory cell in a subsequent multi-phase program operation following the present multi-phase program operation. Results of the program verify phase, and contents of the latch at a start of the present multi-phase program operation, are sufficient to determine the preparation data.

Page buffer circuit

A method is provided for sensing data in a memory device. The memory device includes a block of memory cells coupled to a plurality of bit lines. The method includes precharging the plurality of bit lines to a first level V. The method includes enabling current flow through selected memory cells on the plurality of bit lines to a reference line or to reference lines coupled to a reference voltage. The method includes preventing a voltage change as a result of the current flow on the bit lines from causing a bit line voltage to pass outside a range between the first level and a second level V, where the second level is lower than the first level and higher than the reference voltage. The method includes sensing data in the selected memory cells.

Method and device for reducing coupling noise during read operation

Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.

Architecture for a 3D memory array

A compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot.

Temperature compensation circuit and method for sensing memory

A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages.

Growing community of inventors

Miaoli, Taiwan

Ji-Yu Hung