Samsung Display Co., Ltd.

Samsung Sdi Co., Inc.

Samsung Mobile Display Co., Ltd.

Ji Yong Park

Hye Hyang Park

Sung Ho Cho

Tae Gon Kim

Dong-Yoon So

Ki Yong Lee

Kyong Tae Park

Yong Kim

Jae-Sic Lee

Jin-Yup Kim

Mi Jin Yoon

Woo Young So

Hyun Young Kim

Il Ryong Cho

Provided is a display device including: a plurality of pixels; a plurality of data lines connected to the plurality of pixels; a data driver configured to generate a data voltage applied to the plurality of pixels; a plurality of fan-out lines configured to connect the plurality of data lines and the data driver; a sealant at a periphery of a display area in which the plurality of pixels and the plurality of data lines are arranged, and configured to seal the display area; a metal layer below the sealant; and a repair line configured to connect the data driver and the metal layer.

Display device

A display device includes a plurality of pixels and a compensation power supply line. The pixels are located at intersections of data lines and gate lines. The compensation power supply line is separated from the data lines. Each of the pixels includes an in-pixel circuit and at least one out-pixel circuit. The in-pixel circuit includes a first transistor, to be controlled based on a data voltage from a corresponding one of the data lines, and a storage capacitor connecting the first transistor and a first node. The at least one out-pixel circuit receives a compensation voltage from the compensation power supply line and provides the compensation voltage to the first node.

An organic light-emitting display includes a first substrate which includes a pixel region, and an encapsulation region which surrounds the pixel region, an organic light-emitting device which is located in the pixel region, a sealant which is located in the encapsulation region, and a dummy metal which is interposed between the first substrate and the sealant, where the encapsulation region includes a first encapsulation region and a second encapsulation region which is adjacent to the first encapsulation region, and the dummy metal is located in the first encapsulation region.

Organic light-emitting display

An organic light emitting display device includes a substrate including a display area and a non-display area, a plurality of scan lines extended in a first direction on the substrate, a plurality of data lines extended in a second direction intersecting the first direction, a plurality of first switching elements in the display area, the plurality of first switching elements being connected to the scan lines and data lines, organic emission layers connected to the first switching elements, first dummy lines between corresponding adjacent ones of the plurality of scan lines, the first dummy lines extending in the first direction, second switching elements disposed in the non-display area, the second switching elements being adjacent to first ends of the first dummy lines, and second dummy lines extended in the second direction, the second dummy lines being adjacent to the second switching elements.

Organic light emitting display device and method of repairing the same

An organic light emitting device includes a substrate including a display unit configured to display an image and a peripheral portion surrounding the display unit, a plurality of scan lines on the substrate and extending in a first direction, a plurality of data lines on the substrate and intersecting the scan lines in a second direction, a plurality of pixels at the display unit and connected to the scan lines and the data lines, a repair ring surrounding the display unit, a plurality of driving pads on the peripheral portion and connected to ends of the plurality of data lines, a pair of dummy driving pads on the peripheral portion and connected to ends of the repair ring, and a driving circuit configured to transmit a data signal to the plurality of driving pads and to the pair of dummy driving pads.

Organic light emitting diode display and repairing method thereof

A thin film transistor including a lightly doped drain (LDD) region or offset region, wherein the thin film transistor is formed so that primary crystal grain boundaries of a polysilicon substrate are not positioned in the LDD or offset region.

Thin film transistor with LDD/offset structure

A polycrystalline silicon thin film to be used in display devices, the thin film comprising adjacent primary grain boundaries that are not parallel to each other and do not contact each other, wherein an area surrounded by the primary grain boundaries is larger than 1 &#x3bc;m, a fabrication method of the polycrystalline silicon thin film, and a thin film transistor fabricated using the method.

Polycrystalline silicon thin film, fabrication method thereof, and thin film transistor without directional dependency on active channels fabricated using the same

A polycrystalline silicon thin film to be used in display devices, the thin film having adjacent primary grain boundaries that are not parallel to each other, wherein an area surrounded by the primary grain boundaries is larger than 1 &#x3bc;m, a fabrication method of the polycrystalline silicon thin film, and a thin film transistor fabricated using the method.

A polycrystalline silicon thin film of a TFT in which probabilities P and P for which the maximum number of respective primary crystal grain boundaries for transistors TR and TR arranged perpendicular to each other are contained in active channel regions are P &equals;(D &minus;(Nmax &minus;1)*Gs )/Gs and P &equals;(D &minus;(Nmax &minus;1)*Gs )/Gs : where P or P is not 0.5, D &equals;L cos &thgr;, W sin &thgr;, D &equals;L cos&thgr;&plus;W sin &thgr;, L and L are lengths of active channels, and W and W are widths of the active channels, of the transistors TR and TR , Nmax and Nmax are the maximum numbers of the primary crystal grain boundaries contained in the active channel regions for each of TR and TR , Gs and Gs are crystal grain sizes having a fatal effect on characteristics of each of TR and TR , and &thgr; is an angle in which the primary crystal grain boundaries are inclined perpendicular to an active channel direction of the respective transistors TR and TR

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Suwon, South Korea

Ji Yong Park