Samsung Electronics Co., Ltd.

Ji-yong Chun

Eung-sun Kim

Ki-ho Kim

Kang-min Lee

Kwang-Bok Lee

Hyoung-woon Park

Yeon-kyoon Jeong

An apparatus for searching for a cell and a method of acquiring a code unique to each cell in an asynchronous wideband Direct-Sequence Code Division Multiple Access (DS/CDMA) receiver, wherein the cell searching apparatus searches for a cell based on a received asynchronous wideband DS/CDMA signal in a receiver, the apparatus including a code group identifying unit for estimating and compensating for a frequency error between the synchronous channel and an internally generated primary synchronization code, estimating and compensating for channel degradation which the synchronous channel has experienced, and performing correlation on the compensated synchronous channel and available secondary synchronization codes, thereby identifying the code group; and a scrambling code identifying unit for performing correlation on a plurality of scrambling codes belonging to the code group, thereby obtaining a scrambling code unique to each cell.

Apparatus for searching for a cell and method of acquiring code unique to each cell in an asynchronous wideband DS/CDMA receiver

An apparatus for acquisition of an asynchronous wideband direct-sequence/code division multiple access signal, which acquires a long code from a direct-sequence/code division multiple access control channel signal, in which a common short code, and the long code are transmitted within one frame, and a group identification code indicating a code group, to which a base station belongs, are combined and transmitted with the common short code, includes: a long code masking correlation portion; a differentially coherent combining portion; a code group and frame timing acquisition portion; and a long code acquisition portion for acquiring the long code by correlating the long codes belonging to the acquired code group and the received long code, respectively.

Apparatus for acquisition of asynchronous wideband DS/CDMA signal

Acquisition of initial code synchronization in a receiving system for a code division multiple access (CDMA) signal is realized by producing a complex digital signal having K components by sampling an analog signal derived from the received CDMA-modulated signal. Components of the complex digital signal are correlated with N code phases. The energies of these correlated values are examined, in parallel, to determine whether the ratio of the maximum energy within the block to the average energy in the block equals or exceeds a predetermined threshold. If so, this is a valid maximum, and the code synchronization is complete. If not, further components of the complex digital signal are correlated with another set of N code phases, and are examined in the same manner. Accordingly, reliable determination as to whether code synchronization has been achieved can be realized with minimal influence of channel distortion in a CDMA received signal.

Method and apparatus for acquiring code synchronization in a CDMA communication system

A code division multiple access (CDMA) demodulating method and demodulator employing the demodulating method, the CDMA demodulating method including the steps of: (a) sequentially-storing all input data, which are over-sampled by M-fold and go through a number (N) of paths, in a predetermined first memory, where M and N are predetermined positive integers; (b) generating PN codes for each of the N paths and storing the PN codes in a predetermined second memory; (c) generating and sequentially-storing traffic walsh codes of one period, which correspond to a processing gain L, in a predetermined third memory; (d) multiplying a complex-conjugated value with one of the values stored in the first memory and one of the values stored in the second memory; (e) performing a control operation for storing the PN codes in a predetermined address of the second memory and a control operation for outputting data for each of the N paths from the first, second, and third memories; (f) multiplying the resultant value of the step (d) with the traffic walsh codes of a corresponding path of data stored in the third memory; (g) cumulatively summing the resultant value of the step (f) L times for each of the N multi-paths to be processed, where L corresponds to the processing gain; (h) complex-conjugating the resultant value of the step (d) by cumulatively adding the resultant value of the step (d) X times for each of the N multi-path to be processed, where X corresponds to the data bit number of the walsh codes; (i) obtaining a number (N) of data by inputting the resultant value of the step (f) and the resultant value of the step (h) and multiplying the resultant value of the step (f) with the resultant value of the step (h); (j) sequentially-obtaining a number (N) of values by sequentially-inputting the number (N) of data obtained in the step (i) and taking only real values; (k) cumulatively summing the data obtained in the step (i) N times; and (l) deciding bit values based on logic values identified by identifying the logic values of the result of the step (k), whereby the complexity of the system and the power consumption may be reduced in terms of the number of necessary devices by allowing for suitable downloading of software and performing a demodulation operation in a processor.

CDMA demodulating method and demodulator

An apparatus for recovering timing using an equalizer of an E2PR4ML method and a method therefor and a last data judging apparatus. The timing recovery apparatus includes a sampling unit for sampling a reproduced signal and an equalizing unit for filtering the signal sampled by the sampling unit so as to output as a target signal E2PR4ML for detecting a timing error signal using the target signal output from the equalizing unit, phase synchronizing the detected timing error signal, and providing the phase-synchronized signal as a clock signal of the sampling unit. The timing recovery apparatus also includes a feedback filter using predetermined binary data as an input, an adder for adding the output signal of the feedback filter to the output signal of the equalizing unit and for outputting a new target signal, a data judging unit for detecting binary data on the basis of the new target signal and for generating quaternary data from the detected binary data, and a timing recovery unit for recovering timing by calculating the timing error of the sampling clock using the output signal of the data judging unit.

Timing recovery apparatus and method using equalizer and apparatus for

A digital timing recovery circuit for recovering a sampling clock of a playback signal in digital equipment, provides a fast phase obtaining time, reduces a phase error so as to generate a stable sampling clock and a dead zone effect caused by performing a quantization using a limited number of bits in hardware, and includes an analog-to-digital converter, a phase error detector, a phase error comparator, a loop filter, a reference voltage generator, a digital-to-analog converter and a variable voltage oscillator, to thereby reduce the phase obtaining time by varying the bandwidth of the loop filter according to the phase error size detected by the phase error detector and reduce a sampling phase error caused by noise at a constant state.

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Seoul, South Korea

Ji-yong Chun