Samsung Electronics Co., Ltd.

Ji-yeon Shin

Byung-Hoon Jeong

Jeong-Don Ihm

Jung-June Park

Young-Don Choi

Eun-Ji Kim

Jonghwa Kim

Daehoon Na

Yong-Ju Kim

Young-ei Cho

A memory package includes; a first memory chip including first memory pads, and a buffer chip including first buffer pads respectively connected with the first memory pads and second buffer pads connected with an external device. The buffer chip respectively communicates signals received via the second buffer pads to the first buffer pads in response to a swap enable signal having a disabled state, and the buffer chip swaps signals received via the second buffer pads to generate first swapped signals, and respectively communicates the first swapped signals to the first buffer pads in response to the swap enable signal having an enabled state.

Memory package, storage device including memory package, and storage device operating method

A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.

Non-volatile memory device

Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.

Nonvolatile memory including duty correction circuit and storage device including the nonvolatile memory

A non-volatile memory device includes an output driver to output a data signal. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.

A management server is provided. The management server includes a communication interface unit configured to receive user environment information from a plurality of wearable apparatuses located in a preset space, an analyzer configured to analyze an environment state of the preset space based on a plurality of pieces of the received user environment information regarding the plurality of wearable apparatuses and determines an operation state of a common device located in the preset space according to the analyzed environment state, and a controller configured to control the communication interface unit so as to operate the common device according to the determined operation state.

Growing community of inventors

Anyang-si, South Korea

Ji-yeon Shin