Samsung Electronics Co., Ltd.

Ji-woon Park

Hyun-suk Lee

Ji-won Yu

Hyung-suk Jung

Jin-Su Lee

Byung-Ho Kim

Kwang-Soo Park

Hee-Sook Park

Woong-hee Sohn

Sun-ki Yun

Gi-hee Cho

Jin-an Lee

A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

Methods of manufacturing semiconductor devices

A semiconductor device includes a lower electrode structure, an upper electrode structure, and a dielectric layer between the lower and upper electrode structures and on side surfaces and an upper surface of the lower electrode structure. The lower electrode structure includes a first lower electrode pattern having a cylindrical shape, a barrier layer on the first lower electrode pattern, and a second lower electrode pattern in a space defined by the barrier layer.

Semiconductor device

Provided is an electronic apparatus capable of improving time margin. The electronic apparatus includes: a base substrate including a substrate base including a plurality of layers and a plurality of wiring layers between the layers; a controller chip and at least one memory semiconductor chip mounted on the base substrate; a signal line disposed in one of the wiring layers and connecting the controller chip to the at least one memory semiconductor chip; and a pair of open stubs disposed in another wiring layer, connected to both ends of the signal line, and extending to face each other with a gap.

Electronic apparatus having package base substrate

A solid state drive (SSD) device includes a first nonvolatile memory package, a second nonvolatile memory package, and a controller. The first nonvolatile memory package includes a first buffer chip and a plurality of first nonvolatile memory chips. The second nonvolatile memory package includes a plurality of second nonvolatile memory chips. The controller controls the first nonvolatile memory package and the second nonvolatile memory package. The first buffer chip communicates a first address signal and a first data with the controller, and selectively communicates the first data with one of the plurality of first nonvolatile memory chips and the plurality of second nonvolatile memory chips based on the first address signal.

Solid state drive devices and storage systems having the same

A data storage device is provided. The data store device includes a first printed circuit board (PCB) comprising a main transmission line formed on at least one surface of the first PCB and/or within the first PCB, a memory controller and a plurality of nonvolatile memory devices. The memory controller is provided on the first PCB. The plurality of nonvolatile memory devices are provided on the first PCB. The plurality of nonvolatile memory devices are connected to the memory controller through a channel and exchange data with the memory controller. The channel includes a data transmission line connecting data pads of the memory controller and the nonvolatile memory devices. The data transmission line comprises the main transmission pattern and an open stub contacting the main transmission pattern. The open stub does not contact any other conductor other than the main transmission pattern.

Data storage device including transmission line having open stub and method of operating the same

A method of manufacturing a semiconductor device, the method including supplying a first reactant to inside a processing chamber into which a substrate has been introduced; controlling a flow of a first purge gas and storing the first purge gas, of which flow has been controlled, in a first storage for a given time period; supplying the first purge gas from the first storage to the inside of the processing chamber after supplying the first reactant; and supplying a second reactant to the inside of the processing chamber after supplying the first purge gas.

Method of manufacturing semiconductor device

Solid state drives may include a controller, a mapping table and a buffer memory. The controller provides a logical address of associated data through a first input-output unit at a first speed and provides the associated data through a second input-output unit at a second speed. The controller may be connected to the first input-output unit and the second input-output unit. The mapping table may be connected to the controller through the first input-output unit. The buffer memory may be connected to the controller through the second input-output unit. The first input-output unit may be physically separated from the second input-output unit. The first speed may be different from the second speed.

Controllers including separate input-output circuits for mapping table and buffer memory, solid state drives including the controllers, and computing systems including the solid state drives

An on-die termination (ODT) circuit connected to an input buffer that receives a data signal, the ODT circuit includes at least one termination resistor connected to the input buffer and at least one switching device configured to control a connection between the termination resistor and the input buffer. The switching device is turned on or off according to information about the data signal.

On-die termination circuit, a memory device including the on-die termination circuit, and a memory system including the memory device

A memory module includes at least two rows of memory device packages on a substrate and coupled to a control signal line. A first memory device package in a first row is connected to the control signal line at a first point closest to the proximal end of the control signal line and a second memory device in a second row is connected to the control signal line at a second point next closest to the first point. A signal trace length between the first memory device and the second memory device may be greater than a signal trace length between the first memory device package and a third memory device package immediately adjacent the first memory device package in the first row or a signal trace length between the second memory device package and a fourth memory device package immediately adjacent the second memory device package in the second row.

Growing community of inventors

Suwon-si, South Korea

Ji-woon Park