Samsung Electronics Co., Ltd.

Ji Woon Im

Hyun Seok Lim

Dai Hong Kim

Ji Youn Seo

Sung Jin Park

Ik Soo Kim

Byoung Deog Choi

Hyuk Ho Kwon

Yu Seon Kang

Byung Sun Park

Dong Hyeop Ha

Sang Ho Rha

Tae Yong Eom

Byung Ho Chun

Do Hyung Kim

Hauk Han

Jun Sung Lee

Dong Ik Lee

Il Woo Kim

Kwang Chul Park

Ji Ho Uh

Se Mee Jang

Il Jun Jeon

Dae Hun Choi

Je Hak Lee

Min Jae Oh

Bo Ra Nam

A semiconductor memory device includes a cell substrate, a mold structure including a plurality of gate electrodes stacked on the cell substrate, the gate electrodes including a first ground selection line, a second ground selection line and a plurality of word lines, which are sequentially stacked, a channel structure that extends in a vertical direction that crosses an upper surface of the cell substrate and penetrates the mold structure, a partial isolation region that extends in a first direction that is parallel with the upper surface of the cell substrate and partially separates the mold structure, and a ground isolation structure that connects two partial isolation regions adjacent to each other in the first direction, extends in the vertical direction and penetrates the first ground selection line and the second ground selection line, wherein a width of the ground isolation structure increases with distance from the cell substrate.

Semiconductor memory device, method for fabricating the same and electronic system including the same

A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate; a first conductive pattern on the substrate; a second conductive pattern on the substrate and spaced apart from the first conductive pattern; an air spacer between the first conductive pattern and the second conductive pattern; and a quantum dot pattern covering an upper part of the air spacer.

Method for fabricating semiconductor device

A deposition apparatus includes an upper shower head and a lower shower head within a process chamber, the upper shower head and the lower shower head facing each other, a support structure between the upper shower head and the lower shower head, the support structure being connected to the lower shower head to support a wafer, and a plasma process region between the wafer supported by the support structure and the lower shower head, wherein the lower shower head includes lower holes to jet a lower gas in a direction of the wafer, wherein the upper shower head includes upper holes to jet an upper gas in a direction of the wafer, and wherein the support structure includes through opening portions to discharge a portion of the lower gas jetted through the lower holes to a space between the support structure and the upper shower head.

Deposition apparatus including upper shower head and lower shower head

A method of fabricating a semiconductor device and a semiconductor processing apparatus are provided. The method of fabricating a semiconductor device comprises preparing a semiconductor substrate having a front side and a back side, opposing each other, and forming a material layer on the semiconductor substrate. The material layer is formed on at least a portion of the back side of the semiconductor substrate while being formed on the front side of the semiconductor substrate. The material layer formed on the at least a portion of the back side of the semiconductor substrate is removed, while the material layer formed on the front side of the semiconductor substrate remains. A semiconductor process is performed to fabricate the semiconductor device using the material layer remaining on the front side of the semiconductor substrate.

Method of fabricating semiconductor device by removing material on back side of substrate

A substrate support unit according to an example embodiment of the present inventive concept may include a support having an upper surface on which a substrate is disposed; a coupling ring on which an edge of the substrate is disposed, the coupling ring being having an annular shape, wherein the coupling ring is disposed on an edge of the support; and an arm part for raising and lowering the coupling ring and the substrate, wherein the arm part is disposed below the coupling ring and under a portion of the coupling ring, wherein the coupling ring has a first region disposed on the arm part and a second region disposed around the first region, wherein the first region has a thickness greater than that of the second region.

Substrate support unit and deposition apparatus including the same

Semiconductor device and method for fabricating the same

A deposition apparatus for depositing a material on a wafer, the apparatus including a lower shower head; an upper shower head disposed on the lower shower head, the upper shower head facing the lower shower head; and a support structure between the upper shower head and the lower shower head, the wafer being supportable by the support structure, wherein the upper shower head includes upper holes for providing an upper gas onto the wafer, the lower shower head includes lower holes for providing a lower gas onto the wafer, the support structure includes a ring body surrounding the wafer; a plurality of ring support shafts between the ring body and the lower shower head; and a plurality of wafer supports extending inwardly from a lower region of the ring body to support the wafer, and the plurality of wafer supports are spaced apart from one another.

A semiconductor device includes a gate pattern disposed over a lower structure, and including a gate electrode region and a gate pad region extending from the gate electrode region; and a vertical channel semiconductor layer having a side surface facing the gate electrode region of the gate pattern. The gate pad region includes a first pad region having a thickness greater than a thickness of the gate electrode region. The first pad region includes an upper surface, a lower surface opposing the upper surface, and an outer side surface. The outer side surface has a lower outer side surface and an upper outer side surface, divided from each other by a boundary portion. The lower outer side surface extends from the lower surface, and a connection portion of the lower outer side surface and the lower surface has a rounded shape.

Semiconductor device including gate pattern having pad region

A deposition apparatus includes a chamber, a plate in the chamber and configured support a substrate, a deposition unit configured to perform a deposition process in-situ in the chamber, and a UV annealing unit configured to perform a first ultraviolet (UV) and a second ultraviolet (UV) annealing process in-situ in the chamber. The deposition process may include sequentially depositing a first sacrificial layer, a first oxide layer, a second sacrificial layer and a second oxide layer on the substrate. The first UV annealing process may be performed on the first oxide layer after the first oxide layer is deposited. The second UV annealing process may be different from the first UV annealing process and may be performed on the second oxide layer after the second oxide layer is deposited.

Deposition apparatus including UV annealing unit and method for fabricating non-volatile memory device by using the deposition apparatus

A semiconductor device includes a first interlayer insulating layer and a second interlayer insulating layer, and a horizontal conductive pattern interposed between the first interlayer insulating layer and the second interlayer insulating layer. Vertical structures extend through the first interlayer insulating layer, the second interlayer insulating layer, and the horizontal conductive pattern. Each of the first interlayer insulating layer and the second interlayer insulating layer has regions of different impurity concentrations.

Semiconductor device

Growing community of inventors

Hwaseong-si, South Korea

Ji Woon Im