Samsung Electronics Co., Ltd.

Ji Su Kang

Ju Youn Kim

Sang Jung Kang

Yun Sang Shin

A semiconductor device includes a substrate including NMOS and PMOS regions; first and second active patterns on the NMOS region; third and fourth active patterns on the PMOS region, the third active pattern being spaced apart from the first active pattern; a first dummy gate structure on the first and third active patterns; a second dummy gate structure on the second and fourth active patterns; a normal gate structure on the third active pattern; a first source/drain pattern on the third active pattern and between the normal gate structure and the first dummy gate structure; and a first element separation structure between the first and second dummy gate structures and separating the third and fourth active patterns, wherein the first dummy gate structure includes a first dummy insulation gate intersecting the third active pattern.

Semiconductor device

A semiconductor device includes first to sixth active patterns extending in a first direction and spaced apart in the first direction and a second direction; a field insulating layer between the first and second active patterns, an upper surface thereof being lower than upper surfaces of the first and second active patterns; a first gate structure on the field insulating layer and the first active pattern and extending in the second direction; a second gate structure on the field insulating layer and the second active pattern and extending in the second direction; a first separation trench extending between the second and third active patterns and the fifth and sixth active patterns, and a second separation trench extending between the first and second gate structures, wherein a lowest surface of the first separation trench is higher than a lowest surface of the second separation trench.

Growing community of inventors

Seoul, South Korea

Ji Su Kang