Samsung Electronics Co., Ltd.

Ji-soon Park

Gil-heyun Choi

Byung-Lyul Park

Jong-myeong Lee

Ju-Il Choi

In-Sun Park

Jun-bum Shin

Jin-Ho An

Byeong-jun Kim

Hei-seung Kim

Woo-sang Jung

Pil-Kyu Kang

Jong-Won Hong

Deok-Young Jung

Jung-wook Kim

Ji-hwang Kim

Seong-min Son

Kun-sang Park

Son-kwan Hwang

Eung-Joon Lee

Si-Young Choi

Yang-lim Choi

Hyeon-Deok Lee

Woo-Jin Lee

Atsushi Fujisaki

Kyu-ha Lee

Su-hyun Nam

Hyun-seok Lim

Choong-Hoon Lee

Jin-ho Chun

Hyun-Bae Lee

Jin-Gi Hong

Su-Kyoung Kim

Jeong-gi Jin

Byung-Iyul Park

Yong-Ho Hwang

Joo-Hee Jang

Yi-Koan Hong

Jum-yong Park

Hyung-Jun Jeon

Jeehoon Kang

Dave Ahn

Dongok Kang

Kwangkeun Yi

Dong-jin Kang

Jin-yung Kim

Yong-ho Yoon

Kwang-keun Yi

An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer.

Integrated circuit device including through-silicon via structure and method of manufacturing the same

A method of analyzing a program code of an electronic device includes configuring a tree by using a key string included in the program code and; in response to a command to find a specific key being received, performing a predetermined order traversal of the tree by using a string included in the specific key; in response to a node which matches a last string included in the specific key having a leaf node as a result of the predetermined order traversal, returning a value of the leaf node; and analyzing the program code by using the return value.

Method for analysing program code of electronic device and electronic device

An integrated circuit device includes a semiconductor structure, a through-silicon-via (TSV) structure that penetrates through the semiconductor structure and a connection terminal connected to the TSV structure. A metal capping layer includes a flat capping portion that covers the bottom surface of the connection terminal and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that partially covers a side wall of the connection terminal. The metal capping layer may be formed by an electroplating process in which the connection terminal is in contact with a metal strike electroplating solution while a pulse-type current is applied.

Integrated circuit devices having through-silicon vias and methods of manufacturing such devices

A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.

Semiconductor devices and methods of manufacturing the same, and semiconductor packages including the semiconductor devices

Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate. A through-silicon-via and/or a pad can be directly bonded to another through-silicon-via and/or another pad by applying pressure only, and without performing a heat process.

Semiconductor device having metal patterns and piezoelectric patterns

A method for generating a transport stream of a server is provided. The method for generating a transport stream of a server which sends broadcasting content to a client device comprises: scrambling broadcasting content by using a specific key; adding at least one content-encryption message which includes the specific key and a device key for obtaining the specific key from the at least one content-encryption message to the broadcasting content so as to generate a transport stream; and sending the generated transport stream to the client device.

Server, client device, method for generating a transport stream thereof and processing the transport stream thereof

A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer.

Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same

A method and apparatus for detecting a leak of an information resource of a device. Source code is obtained from an application and is analyzed to determine whether at least one information resource from among information resources of a device is transmittable to outside the device by tracking a task performed on the at least one information resource, thereby detecting whether the application is externally leaking an information resource from the device.

Method and apparatus for detecting leak of information resource of device

A method of forming a dielectric layer, the method including sequentially forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate by performing a plasma-enhanced atomic layer deposition process, wherein a first nitrogen plasma treatment is performed after forming the first oxide layer.

Method of forming a dielectric layer having an ONO structure using an in-situ process

Provided are methods of generating and verifying an electronic signature of software data, wherein software data is split into a plurality of blocks, electronic signatures corresponding to each of the blocks are generated, and some of the electronic signatures are randomly selected for verification. Accordingly, a time required for verifying an electronic signature can be reduced while maintaining the advantages of an electronic signature system.

Method and apparatus for generating and verifying electronic signature of software data, and computer readable recording medium thereof

According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.

Method of forming micropattern, method of forming damascene metallization, and semiconductor device and semiconductor memory device fabricated using the same

A conductive pattern structure includes a first insulating interlayer on a substrate, metal wiring on the first insulating interlayer, a second insulating interlayer on the metal wiring, and first and second metal contacts extending through the second insulating interlayer. The first metal contacts contact the metal wiring in a cell region and the second metal contact contacts the metal wiring in a peripheral region. A third insulating interlayer is disposed on the second insulating interlayer. Conductive segments extend through the third insulating interlayer in the cell region and contact the first metal contacts. Another conductive segment extends through the third insulating interlayer in the peripheral region and contacts the second metal contact. The structure facilitates the forming of uniformly thick wiring in the cell region using an electroplating process.

Semiconductor device conductive pattern structures and methods of manufacturing the same

A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.

Non-volatile memory device

Growing community of inventors

Suwon-si, South Korea

Ji-soon Park