Altera Corporation

Zoom Video Communications, Inc.

Zoom Communications, Inc.

Ji Park

Jinyong Yuan

Kar Keng Chua

Bin Hu

Defeng Lu

Vi Dinh Chau

Evgenii Puchkaryov

An apparatus and/or method discloses an automatic call-to-conference elevation ('ACE') capable of facilitating a transition from a phone call to a video conference. An ACE process, in one embodiment, is able to activate an ACE application to elevate user devices from participating in an audio call to a video conference based on a conference selection selected by a meeting initiator, host, or attendee. After identifying the capabilities, attributes, and/or functionalities associated with the user devices in accordance with activation of ACE, a communication network coupling the user devices as meeting attendees is established for facilitating the video conference based on identified capabilities, attributes, and/or functionalities of the user devices. In one aspect, the process is capable of transitioning connections of the user devices from an audio call to a video conference.

Transferring a phone call into a video conferencing session

Method and system for elevating a phone call into a video conferencing session

Structured ASIC circuitry that is intended to be functionally equivalent to a programmed block of FPGA circuitry (e.g., a programmed FPGA LUT) is verified for such functional equivalence by using the specification (logical or physical) for the structured ASIC circuitry as a starting point for an FPGA design project. If the design project results in the same FPGA circuitry as it was intended that the structured ASIC circuitry would be functionally equivalent to, the structured ASIC circuitry has been verified and can be added to one or more libraries of structured ASIC modules that are available for use in providing structured ASIC products that are functionally equivalent to programmed FPGA products.

Methods of verifying functional equivalence between FPGA and structured ASIC logic cells

A method is provided for creating and using a library of known logic elements for facilitating the design of equivalent FPGA, structured ASIC, or other integrated circuits. Each cell in the library corresponds to a circuit element and contains equivalent circuit models of the element for implementation in different integrated circuit technologies. The cells are named and indexed using a library cell key that contains a fixed set of cell properties which uniquely characterize the function of the cell. The cell key can be used to locate cells in the library or in circuit designs, and to verify that the circuit models contained in the cell implement the correct logic function.

Methods for storing and naming static library cells for lookup by logic synthesis and the like

Structured ASICs that are equivalent to FPGA logic designs are produced by making use of a library of known structured ASIC equivalents to FPGA logic functions. Such a library is expanded by a process that searches new FPGA logic designs for logic functions that either do not already have structured ASIC equivalents in the library or for which possibly improved structured ASIC equivalents can now be devised. The new and/or improved structured ASIC equivalents are added to the library, preferably with version information in the case of FPGA logic functions for which more than one structured ASIC equivalent is known.

Growing community of inventors

San Jose, CA, United States of America

Ji Park