Samsung Electronics Co., Ltd.

Ji-hyun Choi

Kyu-Hong Kim

Do-Hyung Lee

Byung-Jin Kang

Yu-Sun Cheong

Byeong-Seok Choi

Gwan-Young Yoo

Byung-keun Hwang

Hae-jeong Lee

Kun-soo Shin

Ju-seon Goo

Chang-gyu Kim

Hyun-tai Hwang

Eun-seok Choi

Hong-Jae Shin

Yeun-bae Kim

Dong-Yoon Kim

Won-joo Kim

U-in Chung

Jun-il Sohn

Won-Chul Bang

Wan-taek Han

Jin-Sang Hwang

Jin-gi Hong

Vladimir Skvortsov

Seok-ji Hong

Chang-Gyu Kim

Min-su Baek

Geung-won Kang

Young-jin Im

Woo-in Joung

Myeong-beom Lee

Chang-kyu Kim

Ju-Son Gou

Display screen or portion thereof with graphical user interface

An apparatus and method to output a musical tone is disclosed. More particularly, disclosed is an apparatus and method to output a musical tone according to motion, which divides a space in which a terminal can move into a plurality of subspaces, and matches the subspaces with different musical tones, so that the terminal can output a musical tone matched with a specific subspace when the terminal has moved into the specific subspace.

Apparatus and method for generating musical tone according to motion

A method and apparatus for monitoring a human activity pattern irrespective of the wearing position of the sensor unit by a user and a direction of the sensor unit are provided. The method for monitoring an inertia movement signal according to a movement of a user using a sensor unit attached to the user; detecting a direction of the sensor unit from the inertia movement signal; detecting a wearing location of the sensor unit by using acceleration and direction; determining the activity pattern of the user from inertia sensors; and delivering physical activity data corresponding to at least one caloric consumption, number of steps, and movement distance.

Method and apparatus for monitoring human activity pattern

A method and apparatus for counting the steps taken by a walker is provide. The method includes detecting an acceleration value generated by a step taken by a walker at every first stated interval, calculating a standard deviation of detected acceleration values at every second stated interval, determining a walking mode corresponding to the calculated standard deviation among first through Nwalking modes as a walking pattern of the walker, in which N is a positive integer that is larger than 1, checking if there is at least one absolute value that is larger than a threshold acceleration value corresponding to the determined walking mode among the absolute values of the detected acceleration values, and incrementing a count value as a step taken by the walker if there is at least one absolute value that is larger than the threshold acceleration value among the absolute values of the detected acceleration values.

Method and apparatus for counting a number of steps taken by walker

A method for planarizing a semiconductor substrate uses a difference in etch selectivity of insulators on the semiconductor substrate. The method comprises the steps of wet-etching the second and first insulating layers at upper edges of the elevated region until portions of the first insulating layer are exposed at the upper edges, forming a third insulating layer on the first and second insulating layers, and wet-etching the third and second insulating layers until an upper surface of the first insulating layer is exposed. During the wet-etching, the second insulating layer is etched faster than the third insulating layer. With this method, the semiconductor substrate has an even surface.

Method for planarizing a semiconductor substrate

A method for forming a microelectronic device includes the steps of forming a spin-on-glass layer on a microelectronic substrate, and forming a capping layer on the spin-on-glass layer opposite the substrate. A masking layer is formed on the capping layer opposite the substrate wherein the masking layer exposes portions of the capping layer and the spin-on-glass layer. The exposed portions of said capping layer and the spin-on-glass layer are etched using the masking layer as an etch mask to thereby form a contact hole through the capping layer and the spin-on-glass layer wherein protruding edge portions of the capping layer extend beyond the spin-on-glass layer adjacent the contact hole. The mask layer is removed, and the protruding edge portions of the capping layer are removed from adjacent the contact hole.

Multiple etch methods for forming contact holes in microelectronic

Isolation methods for integrated circuits use plasma chemical vapor deposition of an insulating layer followed by lift-off to remove at least portions of the insulating layer. In particular, a lift-off layer is formed on an integrated circuit substrate. The lift-off layer and the integrated circuit substrate beneath the lift-off layer are etched to form a trench in the integrated circuit substrate. The trench defines a first region on one side of the trench and a second region that is narrower than the first region on the other side of the trench. Plasma chemical vapor deposition is then performed to form an insulating layer filling the trench, on the first region and on the second region, with the insulating layer on the first region being thicker than on the second region. The insulating layer is then etched to expose the lift-off layer in the second region. The lift-off layer is then lifted off from the first region. Isolation trenches so formed can have improved isolation characteristics and can be planarized with reduced dishing effects.

Trench isolation methods including plasma chemical vapor deposition and

An insulating layer may be fabricated on a microelectronic substrate by spinning a layer of spin-on-glass (SOG) on a microelectronic substrate and curing the SOG layer by irradiating the SOG layer with an electronic beam. Irradiating may take place simultaneously with heating the substrate to a temperature below about 500.degree. C. An underlying and/or overlying capping layer may also be provided. Alternatively, rather than irradiating the SOG layer, an overlying capping layer may be irradiated.

Method of fabricating and curing spin-on-glass layers by electron beam

A method for forming an insulating layer for a microelectronic device includes the steps of forming a conductive pattern on a surface of a microelectronic substrate, and forming a spin-on-glass layer on the surface of the microelectronic substrate covering the conductive pattern. The spin-on-glass layer is baked at a temperature in the range of 400.degree. C. to 750.degree. C., and a moisture blocking layer is formed on the baked spin-on-glass layer. By reducing moisture absorbed from the air into the spin-on-glass layer, a relatively low etch rate and a relatively low dielectric constant can be maintained for the spin-on-glass layer. Related structures are also discussed.

Methods for forming moisture blocking layers

A method for forming a conductive line uses a fluorine doped oxide layer as an insulating layer between conductive lines. The method comprises the steps of: (a) forming a fluorine doped oxide layer on a semiconductor substrate on which a lower structure is formed; (b) etching the oxide layer of the region where a conductive line is to be formed, thereby forming a trench; (c) forming an insulating layer on the overall surface of the resultant substrate; depositing conductive material on the resultant substrate; and (e) etching back the conductive material so that the conductive material is left on the trench only, thereby forming a conductive line. In this method, the conductive line is formed of aluminum-containing material and the insulating layer is formed of silicon dioxide. In the present invention, the insulating layer is interposed between the fluorine doped oxide layer and the aluminum-containing conductive line and thus the conductive line is free from corrosion.

Method for forming conductive line of semiconductor device

The present invention forms a intermediate layer between a conductive layer and BPSG layer. In one embodiment, this intermediate layer is a buffer layer that absorbs excess P ions from the BPSG layer to suppress the formation of bubbles and thereby prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer. In the second embodiment the intermediate layer is a thin nitride layer, which prevents the conductive layer and BPSG layer from being in direct contact with each other to suppress the formation of bubbles and also prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer.

Method for manufacturing semiconductor device by forming insulator-layer

Growing community of inventors

Seoul, South Korea

Ji-hyun Choi