Skhynix Inc.

Seoul National University

Ji Hyo Kang

Kyung Hoon Kim

Jae Hyeok Yang

Gang Sik Lee

Joo Hyung Chae

Sang Yeon Byeon

Dong Hyun Kim

Suhwan Kim

Dae Han Kwon

Gi Moon Hong

Hyun Bae Lee

Shin Hyun Jeong

Sung Kwon Lee

The present technology may include: a control unit configured to generate two or more control signals in response to frequency information; a reference voltage generation unit configured to generate a first preliminary reference voltage and a second preliminary reference voltage; an amplification section configured to compare a first reference voltage and a second reference voltage with a feedback voltage and configured to output a result as a comparison signal; a voltage selection section configured to, in response to a first control signal, among the two or more control signals, selectively output the first preliminary reference voltage and the second preliminary reference voltage as the first reference voltage and the second reference voltage; and an output section configured to adjust a first current amount according to the comparison signal and configured to output a voltage corresponding to the first current amount as a bias voltage.

Bias generation circuit and buffer circuit including the same

A buffer circuit may include a buffer unit including a first resistor connected between a power source terminal and a first node, a first inductor set connected between the first node and a first input terminal, a second resistor connected between the power source terminal and a second node, and a second inductor set connected between the second node and a second input terminal, and a first variable capacitance circuit connected between the first node and the second node, and configured to adjust a first capacitance value according to a plurality of first adjustment signals.

Buffer circuit, semiconductor device, and signal processing system including semiconductor device

A semiconductor apparatus includes a clock distribution network, a data output circuit, and a data input circuit. The clock distribution network receives a system clock signal and drives the system clock signal to a CMOS level and a CML level to signal in different manners. The data output circuit outputs data based on the clock signal driven to the CMOS level. The data input circuit receives data based on the clock signal driven to the CML level.

Semiconductor apparatus performing a plurality of clock signaling operations and semiconductor system including the same

A voltage generation circuit includes a global driver, a local driver, and a local voltage converter. The global driver changes the voltage level of a second voltage line based on the voltage levels of a first boundary voltage and a first voltage line and changes the voltage level of a fourth voltage line based on the voltage levels of a second boundary voltage and a third voltage line. The local driver adjusts the voltage levels of the first and third voltage lines based on the voltage levels of the second and fourth voltage lines. The local voltage converter generates an internal voltage having a voltage level between the voltage levels of the first and third voltage lines.

Voltage generation circuit and semiconductor device using the same

A clock distribution network includes an input control circuit and a clock tree. The input control circuit is configured to generate a control input clock signal based on an input clock signal and a low power mode signal. The clock tree is configured to generate an output clock signal by buffering the control input clock signal. When the low power mode signal is enabled, the input control circuit is configured to change a DC level of the control input clock signal.

Clock distribution network, and semiconductor apparatus and semiconductor system using the clock distribution network

A clock distribution network includes a global clock generation circuit and a data clock generation circuit. The global clock generation circuit generates a first group of division clock signals by dividing a system clock signal, and generates a second group of division clock signals by dividing the first group of division clock signals. The data clock generation circuit generates a first group of data clock signals based on the system clock signal and at least some of the first group of division clock signals, and generates a second group of data clock signals based on at least some of the first group of data clock signals and at least some of the second group of division clock signals.

Clock distribution network, and semiconductor device and semiconductor system including the clock distribution network

A clock doubler includes a first differential gate and a second differential gate. The first differential gate generates an output clock signal from a first clock signal, a first complementary clock signal, a second clock signal, and a second complementary clock signal and adjusts a duty cycle of the output clock signal based on a first bias control signal. The second differential gate generates a complementary output clock signal from the first clock signal, the first complementary clock signal, the second clock signal, and the second complementary clock signal and adjusts a duty cycle of the complementary output clock signal based on a second bias control signal.

Clock doubler and a semiconductor apparatus using the same

A semiconductor apparatus includes a plurality of clock paths, a first selecting circuit, and a multi-phase clock generating circuit. Each of the clock paths generates a corresponding clock signal pair according to an operation mode. The first selecting circuit outputs, as a reference clock signal pair, the corresponding clock signal pair. The multi-phase clock generating circuit generates first internal clock signals based on the reference clock signal pair.

Semiconductor apparatus including a plurality of clock paths and a semiconductor system using the same

A phase correction circuit includes a plurality of signal paths configured to transmit multi-phase signals. The phase correction circuit further includes a loop circuit coupled to the plurality of signal paths, the loop circuit configured to correct phase skew among the multi-phase signals by averaging the phases of two signals which are obtained by synthesizing a signal of each of the signal paths with another signal of a signal path different from the corresponding signal path.

Phase correction circuit, and clock buffer and semiconductor apparatus including the same

A clock distribution network includes a global clock tree and a local clock tree. When the clock distribution network is activated, the local clock tree is first activated, and the voltage levels of first and second output clock signals are set as a common mode voltage level. When the global clock tree is activated, the global clock tree generates first and second global clock signals from first and second input clock signals. The local clock tree generates the first and second output clock signals from the first and second global clock signals.

Clock distribution network, semiconductor device and semiconductor system including the same, and clock distribution method thereof

A clock distribution circuit includes a global distribution circuit, a first local distribution circuit and a second local distribution circuit. The global distribution circuit receives external clock signals and generates internal clock signals and primary reference clock signal set according to the external clock signals. The first local distribution circuit receives the internal clock signals and the primary reference clock signal set and generates a secondary reference clock signal set according to the internal clock signals and the primary reference clock signal set. The second local distribution circuit receives the internal clock signals and the secondary reference clock signal set and generates a thirdly reference clock signal set according to the internal clock signals and the secondary reference clock signal set.

Clock distribution circuit and semiconductor apparatus including the same preliminary class

An amplifier includes an amplification circuit, an equalization circuit, an output circuit, a first gain adjusting circuit, and a second gain adjusting circuit. The amplification circuit changes voltage levels of first and second amplification nodes based on first and second input signals. The equalization circuit changes the voltage levels of the first and second amplification nodes. The output circuit generates an output signal based on the voltage levels of the first and second amplification nodes. The first gain adjusting circuit changes voltage levels applied to the first and second amplification nodes based on the voltage levels of the first and second amplification nodes and a first gain control signal. The second gain adjusting circuit changes a voltage level of the output signal based on a second gain control signal.

Amplifier and receiving circuit, semiconductor apparatus, and semiconductor system using the same

A power domain change circuit includes an input circuit and an output circuit. The input circuit is suitable for operating in a first power domain and generating first and second intermediate processing signals. The output circuit is suitable for operating in a second power domain and generating a final output signal by averaging and combining transition jitter components of the first and second intermediate processing signals.

Growing community of inventors

Icheon-si, South Korea

Ji Hyo Kang