Samsung Electronics Co., Ltd.

Samsung Led Co., Ltd.

Samsung Electro-mechanics Co., Ltd.

Ji Hye Shim

Dong Jin Kim

Woon Chun Kim

Bum Joon Kim

Ha Yong Jung

Seung Hun Chae

Sang-yeob Song

Jae Min Choi

Jae Kul Lee

Sung Taek Woo

Gun Goo Lee

Woon Chui Choi

Sung Keun Park

So Yeon Moon

Jun Heyoung Park

Han Sang Cho

Ki Seok Kim

Changsung Sean Kim

Han Kook Cho

Jong Pa Hong

Woon Ha Choi

Hyung Mi Jung

Sang Duk Yoo

Won Shin Lee

Seong Hyun Yoo

A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and a first encapsulant covering at least a portion of each of the inactive surface and a side surface of the semiconductor chip. A metal layer is disposed on the first encapsulant, and includes a first conductive layer and a second conductive layer, sequentially stacked. A connection structure is disposed on the active surface of the semiconductor chip, and includes a first redistribution layer electrically connected to the connection pad. A lower surface of the first conductive layer is in contact with the first encapsulant and has first surface roughness, and an upper surface of the first conductive layer is in contact with the second conductive layer and has second surface roughness smaller than the first surface roughness.

Semiconductor package

An antenna module includes: a base substrate including a rigid region and a flexible region; an antenna member disposed on one surface of the rigid region of the base substrate and including antenna patterns; and a semiconductor package disposed on the other surface of the rigid region of the base substrate and including one or more semiconductor chips.

Antenna module

A semiconductor package includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and electrically connected to the one or more redistribution layers, an encapsulant disposed on the connection structure and covering at least a portion of the semiconductor chip, and a shielding structure covering at least a portion of the encapsulant. The shielding structure includes a conductive pattern layer having a plurality of openings, a first metal layer covering the conductive pattern layer and extending across the plurality of openings, and a second metal layer covering the first metal layer. The second metal layer has a thickness greater than a thickness of the first metal layer.

Semiconductor package and electromagnetic interference shielding structure for the same

A fan-out semiconductor package includes a frame comprising a plurality of wiring layers electrically connected to one another, and having a recessed portion having a stopper layeraM disposed on a bottom surface of the recessed portion, and a through-hole penetrating through the stopper layer; a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and disposed in the recessed portion such that the inactive surface opposes the stopper layer; an encapsulant covering at least portions of the frame and the inactive surface of the semiconductor chip, and filling at least a portion of the recessed portion; and an interconnect structure disposed on the frame and the active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to the plurality of wiring layers and the connection pad.

Fan-out semiconductor package

A fan-out sensor package includes: a redistribution portion having a through-hole and including a wiring layer and vias; a first semiconductor chip having an active surface having a sensing region of which at least a portion is exposed through the through-hole and first connection pads disposed in the vicinity of the sensing region; a second semiconductor chip disposed side by side with the first semiconductor chip in a horizontal direction and having second connection pads; dam members disposed in the vicinity of the first connection pads; an encapsulant encapsulating the redistribution portion, the first semiconductor chip, and the second semiconductor chip; and electrical connection structures electrically connecting the first connection pads and the second connection pads to the wiring layer or the vias of the redistribution portion.

Fan-out sensor package

A semiconductor package includes a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, an encapsulant encapsulating at least a portion of the semiconductor chip, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer and a via electrically connected to the connection pads of the semiconductor chip, wherein at least a portion of the redistribution layer and the via is formed of a metal layer having a concave portion depressed from a lower surface thereof and filled with an insulating material.

A fan-out sensor package includes: a sensor chip having a first connection pads and an optical layer; an encapsulant encapsulating at least portions of the sensor chip; a connection member disposed on the sensor chip and the encapsulant and including a redistribution layer electrically connected to the first connection pads; through-wirings penetrating through the encapsulant and electrically connected to the redistribution layer; and electrical connection structures disposed on the other surface of the encapsulant opposing one surface of the encapsulant on which the connection member is disposed and electrically connected to the through-wirings, wherein the sensor chip and the connection member are physically spaced apart from each other by a predetermined distance, and the first connection pads and the redistribution layer are electrically connected to each other through first connectors disposed between the sensor chip and the connection member.

A fan-out semiconductor package includes: a core member having a first through-hole and including first and second wiring layer disposed on different levels; a first semiconductor chip disposed in the first through-hole; a second semiconductor chip disposed on the first semiconductor chip in the first through-hole so that a second inactive surface faces a first inactive surface; conductive wires disposed on the core member and a second active surface and electrically connecting second connection pads and the second wiring layer to each other; an encapsulant covering at least portions of the core member, the first semiconductor chip, the second semiconductor chip, and the conductive wires and filling at least portions of the first through-hole; and a connection member disposed on the core member and a first active surface and electrically connecting first connection pads and the first wiring layer to each other.

Provided is a chemical vapor deposition apparatus. The apparatus includes a reaction chamber, a gas introduction unit, and a gas exhaust unit. The reaction chamber includes a susceptor on which a wafer is loaded and a reaction furnace in which the wafer is processed by chemical vapor deposition. The gas introduction unit is disposed at an outer wall of the reaction chamber to supply reaction gas from an outside of the reaction furnace to a center portion of the reaction furnace. The gas exhaust unit is disposed at a center portion of the reaction chamber to discharge the reaction gas to an upper or lower outside of the reaction chamber after the reaction gas is used for a reaction in the reaction furnace. Therefore, the gas density inside the chamber can be kept at a substantially uniform state even when process pressure is increased for growing a high-temperature deposition layer.

Chemical vapor deposition apparatus

A nitride semiconductor light emitting diode (LED) comprises an n-type nitride semiconductor layer; an electron emitting layer formed on the n-type nitride semiconductor layer, the electron emitting layer being composed of a nitride semiconductor layer including a transition element of group III; an active layer formed on the electron emitting layer; and a p-type nitride semiconductor layer formed on the active layer.

Growing community of inventors

Suwon-si, South Korea

Ji Hye Shim