Samsung Electronics Co., Ltd.

Skhynix Inc.

Samsung Sdi Co., Inc.

Sungkyunkwan University

Hyundai Motor Company

Kia Motors Corporation

Seoul National University

Semes Co., Ltd.

Solip Tech Co., Ltd.

Kia Corporation

Ji Hwan Park

Kyoung Ku Kang

Dong Il Han

Chang Soo Woo

Min Hye Kim

Seung Woo Jang

Ji Sun Im

Myeong Jae Park

Byung Kuk Yoon

Jun Il Moon

Kyung Hoon Kim

Sang Won Lee

Jae Wook Jeon

Ildo Kim

Ser Hoon Lee

Seungwon Choi

Ha Jun Jeong

Jongseong Choi

Suk Hyun Seo

Jae Hoon Cha

Sukhwan Lim

Kyuyul Choi

Se Ra Jeong

Young-Hoo Kim

Young Jun Park

Young Jun Ku

Seung Min Shin

Pil Kyun Heo

Kun Tack Lee

Young Bok Lee

Sang Jin Park

Sang Jine Park

Joon Ho Won

Kyoung Doug Min

Jin Yeong Sung

Seok Woo Choi

Hae Won Choi

Ji Hoon Jeong

Sang Muk Oh

Jang Jin Lee

Koriakin Anton

Chi Heon Song

Seok Won Cho

An apparatus for processing a substrate includes a process chamber; a support which is placed inside the process chamber and supports the substrate; a fluid supplier which supplies fluid into the process chamber; and a controller configured to perform a compressing step to bring the fluid into a supercritical phase inside the process chamber, in which the compressing step includes a continuous first section and second section, the fluid supplier includes a first portion and a second portion, and the controller supplies the fluid into the process chamber at a first speed during the first section using the first portion, and supplies the fluid into the process chamber at a second speed higher than the first speed during the second section using the second portion.

Apparatus and method for processing substrate

A command address control circuit includes a command decoding circuit, an error decision circuit, and a shifting circuit. The command decoding circuit detects a type of command address signal set in synchronization with a reference clock signal. The error decision circuit detects whether an error is present in the command address signal set, and generates a block signal based on the type of command address signal set and the results of the detection of an error. The shifting circuit outputs the command address signal set as an internal command address signal set based on the reference clock signal and the block signal.

Command address control circuit, and semiconductor apparatus and semiconductor system including the command address control circuit

Provided are image signal processing apparatuses and methods for operating the same. In an embodiment, the image signal processing apparatus is configured to receive, from an image sensor device, an input image. The apparatus is further configured to perform a binning and crop operation on the input image to generate a first image. The apparatus is further configured to perform a Bayer domain processing on the first image to generate a second image. The apparatus is further configured to perform RGB domain processing on the second image to generate a third image. The apparatus is further configured to perform YUV domain processing on the third image to generate an output image. The YUV domain processing comprises at least one of a spatial de-noising operation, a temporal de-noising operation, a motion compensation operation, a tone mapping operation, a detail enhance operation, and a sharpening operation.

Image signal processor, operation method of image signal processor, and image sensor device including image signal processor

A semiconductor apparatus includes a command address control circuit. The command address control circuit is configured to receive a row command address signal and a column command address signal, and is configured to selectively invert the row command address signal and the column command address signal based on a logic level of at least one bit of the row command address signal.

Command address control circuit and semiconductor apparatus and semiconductor system including the command address control circuit and semiconductor apparatus

In an embodiment of the present disclosure, an integrated circuit includes: a first interface suitable for receiving first to Ndata, where N is an even number equal to or greater than 2, and first to Nmulti-phase clocks; an interface conversion circuit suitable for generating serial data based on the first to Ndata that are received through the first interface, and generating a data strobe signal for strobing the serial data based on the first to Nmulti-phase clocks that are received through the first interface; and a second interface suitable for receiving the serial data and the data strobe signal.

Integrated circuit and memory system

A device and a method for controlling autonomous driving are provided The device includes non-transitory memory storing instructions executable to control an autonomous driving; and a processor configured to execute the instructions to determine whether a collision has occurred using an acceleration sensor mounted on an airbag control unit during the autonomous driving, determine a collision direction based on a change in acceleration of three axes obtained by the acceleration sensor, and perform an emergency action by controlling at least one of longitudinal direction travel or transverse direction travel based on the collision direction.

Device and method for controlling autonomous driving

An apparatus and method for treating a substrate are provided. The apparatus includes at least one first process chamber configured to supply a developer onto the substrate; at least one second process chamber configured to treat the substrate using a supercritical fluid; a transfer chamber configured to transfer the substrate from the at least one first process chamber to the at least one second process chamber, while the developer supplied in the at least one first process chamber remains on the substrate; and a temperature and humidity control system configured to manage temperature and humidity of the transfer chamber by supplying a first gas of constant temperature and humidity into the transfer chamber.

Apparatus and method for treating substrate including process chambers and transfer chamber

Disclosed is a memory device including an error logic unit suitable for determining whether an error is present in command signals to generate a command error signal; a replica delay circuit suitable for replicating a delay value of the error logic unit and generating an input strobe signal by delaying a strobe signal of the command signals; an output strobe signal generation circuit suitable for generating an output strobe signal activated after a command error latency elapses from a time point at which the command signals are received; and a pipe circuit suitable for receiving and storing the command error signal in response to the input strobe signal and outputting the stored command error signal in response to the output strobe signal.

Memory device

A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.

Data input circuit and memory device including the same

A clock generator circuit includes: first to Nnodes, where N is an even number equal to or greater than 2; and a parallel-to-serial conversion circuit suitable for parallel-to-serial converting signals of the first to Nnodes to output a clock through an output node, wherein, in an activation section of the clock, the signals of even-numbered nodes among the first to Nnodes have a first level, and the signals of odd-numbered nodes among the first to Nnodes have a second level which is different from the first level, and wherein, in a deactivation section of the clock, the signals of the first to Nnodes have the same level.

Clock generator circuit and integrated circuit including the same

A delay circuit includes a first delay line suitable for delaying a first clock by a delay value that is adjusted based on a delay control code; a delay control circuit suitable for comparing a phase of the first clock delayed through the first delay line with a phase of a second clock to generate the delay control code; and a second delay line having, based on a delay control code, a delay value corresponding to a half of the delay value of the first delay line.

Delay circuit and phase interpolator

Disclosed herein is a method of predicting engine knocking, which includes calculating initial pressure in cylinder based on operating data and pressure in intake manifold measured using manifold absolute pressure sensor, calculating pressure at spark timing in the cylinder by interpreting compression process as polytropic process based on the calculated initial pressure in the cylinder, calculating heat release rate for individual operating conditions based on the calculated pressure in the cylinder at spark timing, calculating pressure change in the cylinder based on the calculated heat release rate, calculating unburned gas temperature in adiabatic compression process based on the calculated pressure change in the cylinder, and determining whether knock occurs by calculating ignition delay based on the calculated unburned gas temperature and calculating unburned gas mass fraction at crank angle at the end of the ignition delay.

Method of predicting occurrence of engine knocking

Provided are a window film composition, a flexible window film formed therefrom and a flexible display device containing the same, the composition comprising: a crosslinking agent represented by RX-X&#x2014;Z&#x2014;Y-RY (RX and RY each independently represent a glycidyl group, a glycidyl group-containing functional group, an alicyclic epoxy group or an alicyclic epoxy group-containing functional group); an epoxy group-containing siloxane resin; and an initiator.

Window film composition, flexible window film formed therefrom and flexible display device containing same

Provided are: a composition for a window film, containing a silicone resin comprising chemical formula 1 below, a cross-linking agent, and an initiator; a window film formed therefrom; and a flexible display device comprising the same. (R1SiO)(SiO-Q-SiO)(RSiO)(In chemical formula 1, R1 and R2 are each independently a cycloaliphatic epoxy group, a cycloaliphatic epoxy group-containing functional group, a glycidyl group, or a glycidyl group-containing functional group; Q is R3 or -A1-T-A2-; R3 is a substituted or unsubstituted C1 to C10 alkylene group, or a substituted or unsubstituted C6 to C30 arylene group; A1 and A2 are each independently a single bond, or a substituted or unsubstituted C1 to C5 alkylene group; T is a mono- or polyalkylene oxide group, or an imide group-containing functional group; and 0&#x3c;x&#x3c;1, 0&#x3c;y&#x3c;1, 0&#x2264;z&#x3c;1, and x+y+z=1.

Composition for window film, flexible window film formed therefrom, and flexible display device comprising same

Growing community of inventors

Suwon-si, South Korea

Ji Hwan Park