Samsung Electronics Co., Ltd.

Ji-hwan Choi

Jong-Ho Park

Woo-Sik Kim

Chang-Won Choi

Shin-woo Nam

Dae-hyuk Chung

Bum-su Kim

Yeo-cheol Yoon

A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns. In the semiconductor device manufacture, in forming undercut regions which define the chamfered upper edges of the metal silicide layer patterns, isotropic dry etching is carried out, wherein the isotropic dry etching can be performed simultaneously with ashing of photoresist patterns, or immediately after the ashing process in the same chamber. In either case, after the ashing of the photoresist patterns, an isotropic wet etching can be carried out immediately after performing an existing stripping process, so as to form the undercut regions.

Methods of manufacturing semiconductor devices having chamfered silicide layers therein

Semiconductor device having chamfered silicide layer and method for manufacturing the same

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Seoul, South Korea

Ji-hwan Choi