Skhynix Inc.

Ji Hun Choi

Jeong Hyun Kim

Sung Ju Yoo

Byong Woo Ryu

Son Hong Min

Min Su Son

A storage device of the present disclosure includes a memory device configured to store a plurality of address maps indicating a mapping relationship between a logical address and a physical address, and a memory controller configured to, when the storage device is in a power on state from a power off state, determine a priority rank of each of the plurality of address maps based on file attribute information received from a host and sequentially load the plurality of address maps according to the priority rank.

Memory controller, storage device, and method of operating the same

A heat management circuit may include a throttling circuit configured to cool, for a predetermined time amount, at least one semiconductor functional circuit, which is designed to perform a predetermined function, when a plurality of first temperature signals respectively transmitted from a plurality of temperature sensors installed in the semiconductor functional circuit satisfy a throttling condition; and an analysis unit configured to receive, after lapse of the predetermined time amount, a plurality of second temperature signals from the respective temperature sensors, determine whether the cooling is successful or fails, and detect a temperature sensor having outputted a second temperature signal of abnormal value when the cooling is determined to fail.

Heat management circuit, method for operating the same, and electronic device and data processing apparatus including the same

Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, the memory system may receive a default enabled information from the host. The default enabled information indicates whether the host maintains a configuration of a host memory buffer in the host and target data stored in the host memory buffer when the memory system is in a low power mode state in which power supplied from the host is cut off.

Memory system and operating method supporting fast boot using host memory buffer and default enabled information

A memory controller includes a buffer, a prefetch controller, and a boot controller. The buffer stores workload information including a history of an expected I/O request expected to be received from a host during booting operation. The prefetch controller is configured to, before a target I/O request is received from the host after start of booting, read expected data corresponding to the expected I/O request from memory devices based on workload information, and store the expected data in the buffer. The boot controller updates the workload information based on the target I/O request depending on whether target data corresponding to the target I/O request is included in the expected data, and stores updated workload information in an area in which data is readable with a minimum number of accesses from a plurality of the memory devices.

Memory controller performing booting operation and method of operating the same

A data processing system may include a storage device configured to: transmit, to an exterior, prediction information, for each power mode, that indicates a predicted time for performing a background operation for managing a memory device; and perform the background operation in an idle state of the storage device by switching to a corresponding power mode in response to a power mode control signal that is received in the idle state; and a control device configured to: determine a power mode of the storage device and an idle time for the idle state during which the background operation is performed based on the prediction information; transmit the power mode control signal to the storage device; and suspend, during the idle time, execution of a command processing request transmitted to the storage device.

Data processing system, operation method thereof, and storage device therefor

A host device includes a Host Memory Buffer (HMB) including a plurality of memory areas, each memory area configured to store data provided from a storage device which is in communication with the host device, and a host controller configured to generate reliability information of each of the plurality of memory areas, and in communication with the storage device to provide the reliability information to the storage device.

Growing community of inventors

Gyeonggi-do, South Korea

Ji Hun Choi