Skhynix Inc.

Ji Hoon Nam

Eui Cheol Lim

Sang Eun Je

A semiconductor memory apparatus may include: a data adjusting circuit configured to conditionally adjust a weight data value for a MAC (Multiplication and ACcumulation) operation based on comparing the weight data value to a reference data value, and generate flag information indicating whether the weight data value has been adjusted; a memory cell array circuit configured to store the adjusted weight data value outputted from the data adjusting circuit; and a data calculation circuit configured to recover, on the flag information, a result based on the weight data value from a result based on the adjusted weight data value to perform the MAC operation on an input data value and the weight data value.

Semiconductor memory apparatus and operating method thereof

A data processing system including a shared memory; a host processor configured to possess an ownership of the shared memory, and process a first task by accessing the shared memory; a processor configured to possess the ownership transferred from the host processor, and process a second task by accessing the shared memory; and a memory controller coupled among the host processor, the processor, and the shared memory, and configured to allow the host processor or the processor to access the shared memory according to the ownership.

Memory system adjusting check period for remaining throughput and data processing system including the memory system

A calculation circuit may include a plurality of calculator groups constituting a systolic array composed of a plurality of rows and columns, wherein calculator groups included in each of the rows propagate a data value set through a single data path corresponding to the row in a data propagation direction, and propagate a plurality of drain value sets through a plurality of drain paths corresponding to the row in a drain propagation direction, and wherein a calculator group of the calculator groups included in each of the rows comprises a plurality of MAC (Multiplier-Accumulator) circuits, and the MAC circuits generate drain values respectively included in the drain value sets at the same time. The calculator groups included in each column may further propagate a weight value set corresponding to the column through a plurality of weight data paths corresponding to the column.

Calculation circuit and deep learning system including the same

Data processing system accessing shared memory by using mailbox

A data processing system includes a host device and a data storage device. The host device is configured to select a speed mode of a memory bandwidth based on a network model, or a batch size, or both. The data storage device includes an accelerator configured to change a structure of a processing element (PE) array by controlling transmission paths of first input data and second input data that are input to the PE array based on the speed mode of the memory bandwidth. Computing power and memory power of the accelerator are adjusted according to the selection of the speed mode.

Data storage device, data processing system, and acceleration device therefor

A device includes a first memory including a plurality of memory dice that are arranged vertically to each other, a second memory of a second type, and a controller die that transfers first data between the first memory and a first internal memory of a processor using a first interface and that transfers second data between the second memory and a second internal memory of the processor using a second interface. The first and second memory types are different types of memories. The first and second interfaces are different from each other. The first and second internal memories are different from each other.

Memory device, processing system, and method of controlling the same

A semiconductor apparatus may include a storage device including a data area and a code area and storing program codes provided from a host device in the code area, a plurality of unit processors, each of the plurality of unit processors including an internal memory, and a main control component configured to receive an operation policy, which includes a processor ID, a code ID, and a code address, from the host device and to control the plurality of unit processors based on the operation policy. The processor ID is an identifier for each of the plurality of unit processors, the code ID is an identifier for each of the program codes, and the code address indicates a position of the code area where each of the program codes is stored.

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Icheon, South Korea

Ji Hoon Nam