Dongbu Hitek Co., Ltd.

Ji-Ho Hong

A method of forming an isolation layer in a semiconductor device is disclosed, by which breakdown voltage and PN junction leakage characteristics of the isolation layer are enhanced. Embodiments include depositing a pad nitride layer over a semiconductor substrate, reducing the thickness of the pad nitride layer by etching a portion of the pad nitride layer, forming a tetraethyl orthosilicate (TEOS) oxide layer over the remaining pad nitride layer, forming a trench by selectively removing the tetraethyl orthosilicate oxide layer and the pad nitride layer over an isolation area of the semiconductor substrate, depositing an high density plasma oxide layer over the substrate to fill the trench, and forming an isolation layer by planarizing the high density plasma oxide layer and the tetraethyl orthosilicate oxide layer.

Method of forming isolation layer in semiconductor device

Provided is a monitoring pattern for a silicide that may include a plurality of poly pads, a plurality of N-well regions and P-well regions, active regions, and a poly gate line. The plurality of poly pads are disposed on a semiconductor substrate. The plurality of N-well regions and P-well regions are disposed in a single line between the poly pads. The active regions are disposed on the N-well and the P-well regions. The poly gate line electrically connects the active regions to the poly pads and has a configuration permitting it to pass through the active regions a plurality of times.

Monitoring semiconductor device and method of manufacturing the same

A test element group for monitoring leakage current in a semiconductor device and a method of manufacturing the same are disclosed. The test element group for monitoring leakage current in a semiconductor device includes device isolation layers formed over a first conductivity type semiconductor substrate. A second conductivity type well may be formed over the first conductivity type semiconductor substrate. First conductivity type impurity regions may be formed in first active areas between the device isolation layers in the second conductivity type well. Monitoring contacts may be formed within the first active areas to monitor leakage current, using layout data such that a distance from each of the monitoring contacts to a border of each of the first active areas is set to have an allowable minimum value under a predetermined design rule. Accordingly, the test element group can monitor leakage current caused by PN junction diodes formed by junction of the impurity regions and the well in the active areas in a semiconductor device or misalignment of contacts, and can accurately monitor micro-leakage current in a semiconductor device during manufacturing.

Test element group for monitoring leakage current in semiconductor device and method of manufacturing the same

A test module for measuring electrical characteristics of a semiconductor device includes a plurality of shallow trench isolation (STI) layers formed over a semiconductor substrate. An active area includes not only an extended part enclosing the STI layers but also a plurality of minute line-width parts isolated by the STI layers. A gate oxide layer is formed over the STI layers and the active area. A gate electrode is formed over the STI layers and the minute line-width parts of the active area with interposing the gate oxide layer. An interlayer insulating layer, a metal wiring layer, a contact plug, and test pads allow non-destructive testing of the semiconductor device.

Test module for semiconductor device

A method of forming a metal line in a semiconductor device is disclosed. The method of forming a metal line in a semiconductor device includes forming an interlayer insulating film over a substrate. A via hole may be formed by selectively patterning the interlayer insulating film. A metal film may be formed over a surface of the interlayer insulating film including an inner portion of the via hole. The inner portion of the via hole may be filled with copper. A copper layer exposed over the surface of the interlayer insulating film may be deplated using reverse current to form a copper metal line and a recess region over the copper metal line. An upper insulating film may be formed over the surface of the interlayer insulating film including the recess region by deposition. An insulating cap layer may be selectively formed over only the recess region on the copper metal line by etching the upper insulating film. The upper insulating film and the insulating cap layer may be made of a compound selected from a group including SiN, SiCN and SiOC. An upper insulating film may be deposited over the surface of the interlayer insulating film using a thermal deposition method or a plasma deposition method.

Method of forming metal line in semiconductor device

A semiconductor memory device includes a first active region formed having a first portion extending laterally and second portion extendedly vertically upward from a central portion of the first portion; a second active region formed spaced from the first active region, the second active region having a third portion extending laterally, fourth and fifth portions extending vertically downwardly at distal end portions of the third portion, and a sixth portion extending vertically downwardly at a central portion of the third portion; a first gate formed extending vertically and overlapping the first portion of the first active region and the third portion of the second active regions; a second gate formed extending vertically and overlapping the first portion of the first active region and the third portion of the second active regions; a third gate formed extending in a direction perpendicular to the first and second gates and overlapping of the fourth and fifth portions of the second active region; and a plurality of contacts spaced apart predetermined distances from the gates.

Semiconductor memory device

An image sensor including a second line formed at an upper part of a photodiode region as a transparent electrode for passing light. The second line is composed of a polymeric material having transparency and conductivity.

Growing community of inventors

Suwon-si, South Korea

Ji-Ho Hong