Dongbu Hitek Co., Ltd.

Dongbu Electronics, Co. Ltd.

Ji Ho Hong

Provided are semiconductor devices and methods of fabricating the same. The semiconductor device comprises: a floating gate pattern formed in a cell area of a semiconductor substrate; a dummy floating gate pattern extending from the floating gate pattern into an interface area around the cell area; and a control gate pattern intersecting the floating gate pattern at the cell area of the semiconductor substrate.

Semiconductor device and method of fabricating the same

An image sensor and method of manufacturing the same are provided. According to an embodiment, the image sensor comprises: a circuit including an interconnection on a substrate; a lower electrode on the interconnection; a separated intrinsic layer on the lower electrode; a second conductive type conduction layer on the separated intrinsic layer; and an upper electrode on the second conductive type conduction layer. The separated intrinsic layer can have an inwardly sloping sidewall to focus light incident the photodiode for the unit pixel.

Image sensor and method for manufacturing the same

Disclosed is a method of manufacturing a semiconductor device. The method comprises consecutively depositing and patterning polysilicon and mask material on a substrate to form a polysilicon layer and a mask layer, reducing a width of the polysilicon layer, depositing and etching insulating material on the substrate to form a spacer on a lateral side of the polysilicon layer, and forming a source/drain region in the substrate at sides of the spacer.

Semiconductor device having reduced polysilicon pattern width and method of manufacturing the same

An image sensor and a fabricating method thereof are provided. A pixel area and a peripheral circuit area can have a step difference on a semiconductor substrate. A Complimentary Metal Oxide Semiconductor (CMOS) circuit can be provided on the pixel area, and an interlayer dielectric layer can be provided on the pixel area and the peripheral circuit area. A photodiode can be provided on the interlayer dielectric layer of the pixel area such that the top of the photodiode, or an intrinsic layer of the photodiode, is about even with the top of the interlayer dielectric layer of the peripheral circuit area.

Image sensor

A metal line of semiconductor device and a method of forming the same are provided. An interlayer dielectric (ILD) layer is formed on a semiconductor substrate including a lower line. A via hole is formed in the ILD layer, and a diffusion barrier layer is formed on the ILD layer where the via hole is formed. A copper seed layer and a copper plating layer are repeatedly formed and etched until the hole is completely filled.

Metal line of semiconductor device and method of forming the same

Embodiments relate to a method of forming a copper metal interconnection in a semiconductor device using a damascene process. In embodiments, the method may include forming a damascene pattern in an interlayer dielectric layer on a semiconductor substrate, burying a copper plating layer in the damascene pattern using an ECP method, forming a recess on the copper plating layer buried in the damascene pattern, and forming a barrier metal layer in the recess. Since the barrier metal layer may be locally formed on the copper metal interconnection, it may be possible to prevent the diffusion of the copper although the size of the pattern is small.

Copper metal interconnection with a local barrier metal layer

Disclosed are embodiments relating to a semiconductor device and a method of manufacturing a semiconductor device that may prevent an increase of a dielectric effective constant of the IMD. In embodiments, a semiconductor device may include a substrate having a source/drain area, a gate electrode formed on the semiconductor substrate, a first inter-metal dielectric layer formed on the semiconductor substrate and having a first damascene pattern, a first barrier layer formed on the damascene pattern, a first metal line formed on the first barrier layer, and a first metal capping layer formed in the first damascene pattern.

Semiconductor device and a method for manufacturing the same

Disclosed are embodiments relating to a method of manufacturing a semiconductor device that may improve the yield rate of the semiconductor device. In embodiments, the method may include preparing a substrate including a plurality of conductive patterns, forming first and second insulating layers on the substrate, forming a plurality of via holes by selectively etching the first and second insulating layers, forming a plurality of trenches by selectively etching the second insulating layer in such a manner that the trenches are communicated with the trenches, and forming metal interconnections in the via holes and the trenches. The width ratio of the trench to the insulating layer positioned between adjacent trenches may be in a range of 0.45 to 0.55.

Method of manufacturing semiconductor device

A semiconductor and a method of fabricating the same are provided. The method includes: forming an insulation layer on a substrate; forming a trench by selectively etching the insulation layer; electroplating a copper layer in the trench and on the insulation layer under such conditions that a seam is formed at a top middle portion of the trench; and polishing the copper layer to form a copper metal line with the seam.

Disclosed is a method for monitoring an edge bead removal process for a copper metal interconnection. The method includes the steps of (a) forming a copper metal layer on a semiconductor wafer, (b) performing the edge bead removal (EBR) process of removing the copper metal layer formed in an edge area of the semiconductor wafer, and (c) determining whether copper residues exist by measuring a reflection coefficient Rc of the copper metal layer formed in a center area of the semiconductor wafer and a reflection coefficient (Rb) in the edge area of the semiconductor wafer which is subject to the edge bead removal (EBR) process.

Method for monitoring edge bead removal process of copper metal interconnection

A method for fabricating a semiconductor device to minimize a terminal effect in an ECP process is disclosed. The method for fabricating a semiconductor device to minimize a terminal effect in an ECP process, comprises depositing a barrier metallic layer on the top of a damascene pattern formed through an etching process, forming an Ag seed layer by employing a heating process for the reaction of the surface of the barrier metallic layer and a NHsolution of AgNOand reductive materials in a reactor, plating a Cu layer by using the Ag seed layer through an ECP process and forming a Cu interconnect through an annealing process and a Cu CMP process. The method for fabricating a semiconductor device according to the present invention provides the improvement of uniformity by forming a seed layer with low-resistivity regardless of a thin thickness in order to avoid a terminal effect in an ECP process.

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Hwaseong-si, South Korea

Ji Ho Hong