Samsung Electronics Co., Ltd.

Ji-Ho Cho

Won-Bo Shim

Myong-Jae Kim

Sang-Wan Nam

Yong-Seok Kim

Byoung-taek Kim

Sun-gyung Hwang

Won-Ju Lee

Jong-Mun Choi

Dong-Woo Sohn

Ji-sang Lee

Byung-Soo Kim

Dong-Jin Shin

Seung-Keun Lee

June-Hong Park

Soo-Han Kim

Jong-In Choi

Sang-wan Nam

Hyeok Kang

Myong-Jac Kim

A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.

Nonvolatile memory device and program method of the same

A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, a row decoder in the peripheral circuit region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes memory cells stacked in a direction intersecting a substrate, and is divided into a plurality of sub-blocks configured to be erased independently. The row decoder selects the memory block by units of a sub-block. The control circuit receives a data erase command for a selected sub-block among the plurality of sub-blocks, performs a data read operation on at least one victim sub-block among the plurality of sub-blocks in response to the data erase command, selectively performs a soft program operation on the at least one victim sub-block based on a result of the data read operation, and performs a data erase operation on the selected sub-block after the data read operation is performed and the soft program operation is selectively performed.

Method of erasing data in nonvolatile memory device, nonvolatile memory device performing the same and memory system including the same

An operation method of a nonvolatile memory device for programming memory cells connected to a selected word line, the method including: performing a program operation; suspending the program operation after performing a first portion of the program operation; and resuming the program operation to perform a second portion of the program operation, wherein the program operation is resumed within a reference time after the program operation is suspended.

Operation method of a nonvolatile memory device for controlling a resume operation

A method of operating a memory device includes performing a data read operation on at least one victim sub-block within a memory block containing a plurality of sub-blocks therein, in response to an erase command directed to a selected sub-block within the plurality of sub-blocks. Next, a soft program operation is performed on the at least one victim sub-block. This soft programming operation is then followed by an operation to erase the selected sub-block within the plurality of sub-blocks. This operation to erase the selected sub-block may include providing an erase voltage to a bulk region of a substrate on which the memory block extends, and the at least one victim sub-block may be disposed between the selected sub-block and the substrate.

A three-dimensional (3D) memory device having a plurality of vertical channel structures includes a first memory block, a second memory block, and a bit line. The first memory block includes first vertical channel structures extending in a vertical direction with respect to a surface of a substrate. The second memory block includes second vertical channel structures on the first vertical channel structures in the vertical direction and first and second string selection lines extending in a first horizontal direction and offset in the vertical direction. The bit line extends in the first horizontal direction between the first and second memory blocks and is shared by the first and second memory blocks. The second memory block may include first and second string selection transistors which are each connected to the bit line and the first string selection line and have different threshold voltages from each other.

Three-dimensional memory devices having plurality of vertical channel structures

Provided is a flash memory device. The flash memory device includes: a memory cell storing multi-bit data; a reference bias voltage supply circuit generating a reference bias voltage; an sense amplifier sensing the multi-bit data stored in the memory cell using the reference bias voltage; and a control circuit controlling the reference bias voltage supply circuit. The control circuit controls the reference bias voltage supply circuit to allow the reference bias voltage to be developed according to a change of a main word line voltage applied to the memory cell during a read operation.

Flash memory device having improved read operation speed

A semiconductor memory device includes a memory core; a charge pump circuit providing a high voltage to the memory core; and a charge pump control circuit operating the charge pump circuit by a standby mode and measuring an operation time value of the standby mode. The charge pump control circuit controls the standby mode of the charge pump circuit using the time value.

Semiconductor memory device

A memory cell array, divided into multiple row memory cell arrays, includes multiple memory banks and sense amplifiers. Each of the memory banks includes multiple logical sectors and at least two sub-memory banks of multiple sub-memory banks. The at least two sub-memory banks are included in different row memory cell arrays, and each of the sub-memory banks includes multiple physical sectors. The sense amplifiers are dedicated to the sub-memory banks, respectively.

Memory cell array and non-volatile memory device

A nonvolatile memory device includes a trimming cell array storing trimming data for a plurality of operating modes, a trimming cell sense amplifier sensing the trimming data and a trimming cell latch storing the sensed trimming data. A plurality of trimming circuits performs trimming operations in response to a trimming control signals derived from trimming data. A single temporary trimming control logic unit receives externally provided control data and controls operation of a single summation circuit. The summation circuit controls the operation of the trimming circuits by respectively and selectively varying the trimming control signal provided to each one of the plurality of trimming circuits in response to the externally provided control data.

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Suwon-si, South Korea

Ji-Ho Cho