United Microelectronics Corp.

Untied Microelectronics Corp.

Ji-Fu Kung

Hsin-Ming Hou

Ming-Tsung Yeh

Wei-Lun Hsu

Yan-Hsiu Liu

Ching-Pei Lin

Yao-Pi Hsu

Am-Tay Luy

Yung-Chien Kung

Yu-Cheng Tung

Wai-Yi Lien

Ming-Tsung Chen

Zheng-Yang Li

Chun-Man Li

Chung-Jung Chen

Yi-Cheng Lu

Chin-Chun Huang

Ping-Pang Hsieh

Li-Hsin Yang

Te-Hsuan Chen

Wei-Po Chiu

Nick Chao

Yi-Lin Hung

Chuan-Guei Wang

Neng-Hsing Shen

Chian-Chen Kuo

Chien-Wen Yang

A manufacturing data analyzing method and a manufacturing data analyzing device are provided. The manufacturing data analyzing method includes the following steps. Each of at least one numerical data, at least one image data and at least one text data is transformed into a vector. The vectors are gathered to obtain a combined vector. The combined vector is inputted into an inference model to obtain a defect cause and a modify suggestion.

Manufacturing data analyzing method and manufacturing data analyzing device

An automatic adjustment method and an automatic adjustment device of a beam of a semiconductor apparatus, and a training method of a parameter adjustment model are provided. The automatic adjustment method of the beam of the semiconductor apparatus includes the following steps. The semiconductor apparatus generates the beam. A wave curve of the beam is obtained. The wave curve is segmented into several sections. The slope of each of the sections is obtained. Several environmental factors of the semiconductor apparatus are obtained. According to the slopes and the environmental factors, at least one parameter adjustment command of the semiconductor apparatus is analyzed through the parameter adjustment model.

Automatic adjustment method and automatic adjustment device of beam of semiconductor apparatus, and training method of parameter adjustment model

An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

Integrated circuit structure with semiconductor devices and method of fabricating the same

An operation method and an operation device of a failure detection and classification (FDC) model are provided. The operation method of the FDC model includes the following steps. A plurality of raw traces are continuously obtained. If the raw traces have started to be changed from the first waveform to the second waveform, whether at least N pieces in the race traces have been changed to the second waveform is determined. If at least N pieces in the raw traces have been changed to the second waveform, the raw traces which have been changed to the second waveform are automatically segmented to obtain several windows. An algorithm is automatically set for each of the windows. Through each of the algorithms, an indicator of each of the windows is obtained. The FDC model is retrained based on these indicators.

Operation method and operation device of failure detection and classification model

A remote control device for a manufacturing equipment and a method for detecting manual control are provided. The method for detecting the manual control on the manufacturing equipment includes the following steps. A cursor pattern is created. When the user interface is automatically controlled, a history location of the cursor pattern shown on a user interface of the manufacturing equipment is detected to obtain a location distribution. The location distribution is stored. A current location of the cursor pattern shown on the user interface is detected. If the current location is not within the location distribution, it is deemed that the user interface is manually controlled.

Remote control device for manufacturing equipment and method for detecting manual control

An apparatus for controlling an operation of a machine includes an optical recognition system, a control unit, and a remote control interface. The optical recognition system is configured to monitor and obtain actual operation information displayed on a panel of a processing machine in accordance with an operation time. The control unit is configured to receive the actual operation information and check the actual operation information with expected operation information. The expected operation information is obtained based on an operation model which is already built up corresponding to a current fabrication process. Deviation information between the actual operation information and the expected operation information is determined and converted into a parameter set. The remote control interface receives the parameter set and converts the parameter set into a control signal set to control the operation of the processing machine.

Apparatus and method for controlling operation of machine

For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

Hierarchical wafer lifetime prediction method

A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.

Semiconductor device with epitaxial structures and method for fabricating the same

A stacked semiconductor structure and a manufacturing method for the same are provided. The stacked semiconductor structure is provided, which comprises a first semiconductor substrate, a second semiconductor substrate, a dielectric layer, a trench, a via, and a conductive structure. The first semiconductor substrate comprises a first substrate portion and a first conductive layer on an active surface of the first substrate portion. The second semiconductor substrate comprises a second substrate portion and a second conductive layer on an active surface of the second substrate portion. The trench passes through the second substrate portion and exposing the second conductive layer. The via passes through the dielectric layer and exposes the first conductive layer. The conductive structure has an upper portion filling the trench and a lower portion filling the via. Opposing side surfaces of the upper portion are beyond opposing side surfaces of the lower portion.

Stacked semiconductor structure and manufacturing method for the same

Semiconductor device and method for fabricating the same

A multi-gate transistor device includes a substrate, a fin structure extending along a first direction formed on the substrate, a gate structure extending along a second direction formed on the substrate, a drain region having a first conductivity type formed in the fin structure, a source region having a second conductivity type formed in the fin structure, and a first pocket doped region having the first conductivity type formed in and encompassed by the source region. The first conductivity type and the second conductivity type are complementary to each other.

Multi-gate transistor device

Hierarchical wafer yield prediction method and hierarchical lifetime prediction method

Growing community of inventors

Taichung, Taiwan

Ji-Fu Kung